Arithmetic processing unit and control method for arithmetic processing unit

A method of controlling an arithmetic processing unit, the method comprising:

• the arithmetic processing unit including an instruction decoder which decodes a fetch instruction fetched from a memory to issue an execution instruction;
• a reservation station which temporarily stores the execution instruction issued by the instruction decoder;
• and an arithmetic unit which executes the execution instruction stored in the reservation station, wherein the fetch instruction includes a multi-flow instruction which is divided into a plurality of divided instructions, and a single instruction which is not divided,
• in the instruction decoder,
• N number of slots (N is a positive integer) in a pre-decoder each inputting the fetch instruction, detecting a division number of the multi-flow instruction, and dividing the multi-flow instruction into a plurality of divided instructions;
• N number of slots in a main decoder each decoding the divided instruction and the single instruction to issue an execution instruction corresponding to the divided instruction and the single instruction;
• and
• N−K number of slots (K is a positive number, N>K) in a pre-decoder buffer each temporarily storing instructions in the pre-decoder, further
• the instruction decoder repeating transferring the divided instructions and the single instructions from the N number of slots of the pre-decoder and the N−K number of slots of the pre-decoder buffer to the N number of slots of the main decoder as much as possible in order, and
• when all the divided instructions and all the single instructions in at least the N−K number of slots of the pre-decoder buffer and first K number of slot or slots of the pre-decoder are transferred to the main decoder while the instruction decoder repeats the transferring, the instruction decoder transferring the instructions remaining in the pre-decoder to the pre-decoder buffer, and inputting the next N number of fetch instructions to the N number of slots of the pre-decoder respectively.