Nand raid controller
AssigneeToshiba Memory Corporation
InventorSie Pook LAW
Life of this patent
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Abstract
An array controller for connection between a solid state drive controller and multiple non-volatile storage units is provided. The array controller comprises a plurality of enable outputs, each of which is connected to an enable input of one of the non-volatile storage units, and a buffer in which data to be written into or read from the non-volatile storage units is stored. The array controller further comprises a control unit configured to enable a communication path between the solid state drive controller and one of the non-volatile storage units according to an address received from the solid state drive controller.
Claims19
A memory controller comprising:
- a first controller circuitry that includes a data output connected to a first data bus and at least a first enable output and a second enable output connected to a plurality of first communication paths;
- and
- a second controller circuitry connected to the first controller circuitry via the first data bus and one of the first communication paths and capable of connecting to at least a first non-volatile storage device and a second non-volatile storage device via a second data bus and a plurality of second communication paths, the second controller circuitry including:
- a first buffer for storing data to be written into or read from at least the first or second non-volatile storage devices to be connected to the second controller circuitry,
- a first enable input connected to the first enable output of the first controller circuitry via the one of the first communication paths,
- a third enable output capable of connecting to an enable input of the first non-volatile storage device via one of the second communication paths,
- a fourth enable output capable of connecting to an enable input of the second non-volatile storage device via another of the second communication paths, and
- a first control unit configured to assert one of the third and fourth enable outputs in response to the first enable input being asserted.
A method of performing read and write operations in a memory controller comprising a first controller circuitry capable of connecting to a plurality of non-volatile storage devices by way of a plurality of second controller circuitries, wherein the first controller circuitry has a plurality of enable outputs connected respectively to the second controller circuitries via a plurality of communication paths and a data output connected to each second controller circuitry via a first data bus, said method comprising:
- asserting one of the enable outputs of the first controller circuitry to activate an second controller circuitry connected to the asserted enable output via one of the communication paths;
- transmitting a command and an address from the first controller circuitry to the activated second controller circuitry from the data output via the first data bus;
- at the activated second controller circuitry, determining, based on the transmitted address, one of the non-volatile storage devices targeted by the command;
- and
- transmitting the command to the targeted non-volatile storage device via a second data bus.
Dependencies are inferred from the claim text.