Apparatuses and methods for in-memory operations

An apparatus, comprising:

• a processing in memory (PIM) capable device, comprising:
• an array of memory cells;
• a compute component selectably coupled to a sense line of the array;
• timing circuitry of control circuitry configured to execute an instruction and selectably coupled to the array and the compute component, the timing circuitry configured to control timing of performance of operations using the compute component;
• and
• a sequencer of the control circuitry selectably coupled to the timing circuitry, the sequencer configured to coordinate compute operations;
• and
• a host comprising control logic, the control logic configured to issue a command instruction set including the instruction to the sequencer of the control circuitry on the PIM capable device to initiate performance of a plurality of compute operations.

An apparatus, comprising:

• a processing in memory (PIM) capable device;
• a host comprising control logic, the control logic configured to issue a command instruction set including an instruction to the PIM capable device to initiate performance of a plurality of compute operations;
• and
• a sideband channel for communication between the control logic on the host and the PIM capable device;
• wherein:
• the PIM capable device comprises control circuitry coupled to a compute component, the control circuitry comprising:
• a sequencer configured to receive the instruction via the sideband channel, to execute the instruction, and to coordinate the compute operations;
• timing circuitry configured, responsive to a first command instruction set received from the sequencer, to provide timing to coordinate the performance of the compute operations;
• a row address strobe (RAS) manager configured, responsive to a second command instruction set received from the timing circuitry, to coordinate timing of a sequence of compute sub-operations of a compute operation;
• a RAS component configured, responsive to a third command instruction set received from the RAS manager, to direct performance of the sequence of compute sub-operations, the timing of which is directed by the RAS manager;
• wherein the compute component is configured to perform the sequence of compute sub-operations as directed by the RAS component.