Memory component having internal read-modify-write operation

A memory component comprising:

• a memory bank;
• a command interface coupled to the memory bank, the command interface to receive, from a memory controller, a read-modify-write command, the read-modify-write command having an associated read address indicating a location in the memory bank to access read data;
• a data interface coupled to the memory bank, the data interface to receive write data associated with the read-modify-write command;
• and
• an error correction circuit coupled to the data interface and to the memory bank, the error correction circuit to:
• decode the read data as decoded read data;
• merge the received write data with the decoded read data;
• encode the merged data during a same column cycle interval in which the read data is decoded;
• and
• write the merged data to the location in the memory bank indicated by the read address.

A method of operation in a memory component, the method comprising:

• receiving, from a memory controller, a read-modify-write command, the read-modify-write command having an associated read address indicating a location in a memory bank to access read data;
• receiving write data associated with the read-modify-write command;
• decoding the read data as decoded read data;
• merging the received write data with the decoded read data;
• encoding the merged data during a same column cycle interval in which the read data is decoded;
• and
• writing the merged data to the location in the memory bank indicated by the read address.

A memory component comprising:

• means for receiving, from a memory controller, a read-modify-write command, the read-modify-write command having an associated read address indicating a location in a memory bank to access read data;
• means for receiving write data associated with the read-modify-write command;
• means for decoding the read data as decoded read data;
• means for merging the received write data with the decoded read data;
• means for encoding the merged data during a same column cycle interval in which the read data is decoded;
• and
• means for writing the merged data to the location in the memory bank indicated by the read address.