Memory system including memory device and memory controller, and operating method thereof

An operating method of a memory system, comprising:

• generating a second address based on a first address indicating a defective memory cell among a plurality of memory cells in a memory device;
• sequentially transmitting the first address and a first command corresponding to the first address, and the second address and a second command corresponding to the second address to the memory device;
• and
• writing and reading data to and from the defective memory cell in response to the first address and command and the second address and command which are sequentially inputted.

A memory system comprising:

• a memory device including a plurality of memory cells;
• and
• a memory controller suitable for:
• detecting a defective memory cell among the plurality of memory cells;
• and
• accessing the defective memory cell and another memory cell, among the plurality of memory cells, in response to a command for accessing the defective memory cell,
• wherein the defective memory cell and the another memory cell share the same bit line or the same sense amplifier, and
• wherein the defective memory cell and the another memory cell are on different word lines in the memory device.