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US 2019/0294372 A1Published application
Memory controller, memory system having the same, and method of operating the same
AssigneeSK hynix Inc.
InventorHyun Woo LEE
Life of this patent
Estimating the term…
Abstract
A memory controller includes an interleaving component configured to determine an access sequence of a plurality of memory units based on estimated execution times for the respective memory units to perform an operation, and a processor configured to access the memory units in the determined access sequence to perform the operation in an interleaved manner.
Claims20
A memory controller, comprising:
- an interleaving component configured to determine an access sequence of a plurality of memory units based on estimated execution times for the respective memory units to perform an operation;
- and
- a processor configured to access the memory units in the determined access sequence to perform the operation in an interleaved manner.
A memory system, comprising:
- a plurality of memory units configured to perform an operation in an interleaved manner;
- and
- a memory controller configured to determine an access sequence of the memory units based on estimated execution times for the respective memory units to perform the operation and to access the memory units in the determined access sequence.
A method of operating a memory controller, the method comprising:
- acquiring information about estimated execution times for a plurality of memory units to respectively perform an operation;
- determining an access sequence of the memory units based on the estimated execution times;
- and
- accessing the memory units in the determined access sequence to perform the operation in an interleaved manner.
1 more element
A memory system, comprising:
- a plurality of memory units configured to function as an interleaving group in an initial access sequence to perform an operation;
- and
- a memory controller suitable for:
- reordering the access sequence of the memory units based on estimated execution times for the respective memory units to perform the operation;
- and
- accessing the memory units in the reordered access sequence.
3 more elements
Dependencies are inferred from the claim text.