Energy Conservation for Memory Applications
AssigneeArm Limited
InventorWei Wang
Life of this patent
Estimating the term…
Abstract
Various implementations described herein are directed to an integrated circuit having a cache with memory components that store data with multiple addresses. The integrated circuit may include a controller that communicates with the cache to provide directives to the cache. The integrated circuit may include a refresh circuit that interprets the directives received from the controller to generate interpretation information based on determining one or more particular addresses of the multiple addresses that no longer need refreshing. The refresh circuit may further employ the interpretation information to skip the need for refreshing the one or more particular addresses pointing to the memory components in the cache that no longer need refreshing.
Claims20
An integrated circuit, comprising:
- a cache having memory components that store data with multiple addresses;
- a controller that communicates with the cache to provide directives to the cache;
- a refresh circuit that:
- interprets the directives received from the controller to generate interpretation information based on determining one or more particular addresses of the multiple addresses that no longer need refreshing, and
- employs the interpretation information to skip the need for refreshing the one or more particular addresses pointing to the memory components in the cache that no longer need refreshing.
An integrated circuit, comprising:
- a cache having dynamic random access memory (DRAM) components that store data with multiple addresses;
- a processor that communicates with the cache to send directives to the cache;
- a self refresh circuit that:
- intercepts the directives from the processor,
- determines one or more particular addresses of the multiple addresses that reference instances where retaining data is deemed unnecessary,
- interprets the intercepted directives to generate interpretation data based on determining the one or more particular addresses of the multiple addresses that reference the instances where retaining data is deemed unnecessary, and
- uses the interpretation data to save power by escaping a need for retaining data for the one or more particular addresses of the multiple addresses that point to the DRAM components in the cache that no longer need to retain data.
A method for manufacturing an integrated circuit, comprising:
- fabricating a cache having memory components that store data with addresses;
- fabricating a controller that communicates with the cache to provide directives to the cache;
- fabricating a refresh circuit that is configured to:
- interpret the directives received from the controller to generate interpretation data based on determining one or more particular addresses of the addresses that reference instances where retaining data is deemed unnecessary, and
- employ the interpretation data to skip a need for refreshing the one or more particular addresses pointing to the memory components in the cache that no longer need refreshing.
Dependencies are inferred from the claim text.