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US 2019/0294356 A1Published application
Hybrid memory system
AssigneeMicron Technology, Inc.
InventorsDanilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
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Abstract
An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.
Claims27
An apparatus, comprising:
- a hybrid memory system comprising a first non-volatile memory (NVM) resource and second NVM resource to couple to a host;
- a controller to determine that the first NVM resource or the second NVM resource exhibits a lower write latency than the other of the first NVM resource or the second NVM resource;
- and
- the controller coupled to the hybrid memory system, wherein the controller is configured to:
- assign a sensitivity to a command, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with execution of the command;
- and
- cause the command to be selectively diverted to the first NVM or the second NVM of the hybrid memory system by mapping a logical block address (LBA) associated with a main memory coupled to the hybrid memory to the one of the first NVM or the second NVM that exhibits the lower write latency based, at least in part, on the assigned sensitivity.
4 more elements
An apparatus, comprising:
- a hybrid memory system comprising a first non-volatile memory (NVM) resource and second NVM resource;
- the hybrid memory system to couple to a host;
- and
- a controller to determine that the first NVM or the second NVM exhibits a lower write latency than the other of the first NVM or the second NVM;
- the controller coupled to the hybrid memory system, wherein the controller is configured to:
- identify a particular type of command traffic executed by the host;
- assign a sensitivity to a command, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with execution of the command;
- and
- cause the command traffic to be selectively diverted to the first NVM or the second NVM of the hybrid memory system by mapping a logical block address (LBA) associated with a main memory coupled to the hybrid memory to the one of the first NVM or the second NVM that exhibits the lower write latency based, at least in part, on the identified characteristic and the assigned sensitivity.
6 more elements
A method, comprising:
- assigning a sensitivity to a command, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with execution of the command;
- and
- selectively diverting the command to a flash memory device or the phase change random access memory device of the hybrid memory system by mapping a logical block address (LBA) associated with a main memory coupled to the hybrid memory to the flash memory device or the resistance variable memory device that exhibits the lower write latency based, at least in part, on the assigned sensitivity.
A method, comprising:
- identifying a particular type of command traffic executed by a host;
- assigning a sensitivity to a command, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with execution of the command;
- and
- causing the command traffic to be selectively diverted to a flash memory device or a phase change random access memory device of a hybrid memory system coupleable to the host by mapping a logical block address (LBA) associated with a main memory coupled to the hybrid memory to the flash memory device or the resistance variable memory device that exhibits the lower write latency based, at least in part, on the identified characteristic and the assigned sensitivity.
1 more element
Dependencies are inferred from the claim text.