Single chip multi-die architecture having safety-compliant cross-monitoring capability
AssigneeIntel Corporation
InventorsNabajit Deka, Riccardo Mariani, Asad Azam, Roger May, Prashanth Gadila
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AssigneeIntel Corporation
InventorsNabajit Deka, Riccardo Mariani, Asad Azam, Roger May, Prashanth Gadila
Estimating the term…
Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.
A chip comprising:
A platform comprising:
A chip comprising:
A method of operating a chip, comprising:
Dependencies are inferred from the claim text.