Test Generation Using Testability-Based Guidance
AssigneeMentor Graphics Corporation
InventorsSylwester Milewski, Janusz Rajski, Yu Huang
Life of this patent
Estimating the term…
Abstract
Constant-output-value gates and buffer gates are determined for gates in a circuit design based on a hold-toggle pattern. The hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation. Activation probabilities and observation probabilities are then determined for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates. Finally, test patterns are generated based on the activation probabilities and the observation probabilities.
Claims21
A method, executed by at least one processor of a computer, comprising:
- determining constant-output-value gates and buffer gates for gates in a circuit design based on a hold-toggle pattern, wherein each of the constant-output-value gates represents one or more gates in the circuit design, each of the buffer gates represents one or more gates in the circuit design, and the hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation;
- determining activation probabilities and observation probabilities for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates;
- and
- generating test patterns based on the activation probabilities and the observation probabilities.
One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
- determining constant-output-value gates and buffer gates for gates in a circuit design based on a hold-toggle pattern, wherein each of the constant-output-value gates represents one or more gates in the circuit design, each of the buffer gates represents one or more gates in the circuit design, and the hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation;
- determining activation probabilities and observation probabilities for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates;
- and
- generating test patterns based on the activation probabilities and the observation probabilities.
A system, comprising:
- one or more processors, the one or more processors programmed to perform a method, the method comprising:
- determining constant-output-value gates and buffer gates for gates in a circuit design based on a hold-toggle pattern, wherein each of the constant-output-value gates represents one or more gates in the circuit design, each of the buffer gates represents one or more gates in the circuit design, and the hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation;
- determining activation probabilities and observation probabilities for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates;
- and
- generating test patterns based on the activation probabilities and the observation probabilities.
Dependencies are inferred from the claim text.