Semiconductor device
AssigneeRenesas Electronics Corporation
InventorYoshisato YOKOYAMA
Life of this patent
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Abstract
A semiconductor device includes a memory cell array, a plurality of word lines, a plurality of bit line pairs, a column selection circuit coupling a bit line pair in a selected column in the plurality of bit line pairs to first and second output signal lines on the basis of a column selection signal, and a sense amplifier amplifying the voltage difference between the first and second output signal lines. The semiconductor device further includes: a scan flip flop to which the data can be input via a scan chain; and a voltage setting circuit setting the first and second output signal lines to voltage according to the data held in the scan flip flop in a scan test.
Claims16
A semiconductor device comprising:
- a first memory cell;
- a first bit line pair corresponding to the first memory cell;
- a sense amplifier amplifying a voltage difference between the bit line pairs;
- and
- a scan flip flop coupled with a plurality of flip flops coupled in series,
- wherein the scan flip flop is coupled with the sense amplifier via a voltage setting circuit.
A semiconductor device comprising:
- a memory cell;
- an input selection circuit which receives input of a first control signal, a data to be written in the memory cell, and a data for a scan test, selects the data for a scan test when the first control signal is activated, and selects the data to be written in the memory cell when the first control signal is not activated;
- a first latch circuit to which the data selected by the input selection circuit is input;
- a second latch circuit provided at a post stage of the first latch circuit;
- a third latch circuit to which a second control signal is input;
- a first logic circuit which makes an output signal of the third latch circuit pass when the first control signal is not activated;
- and
- a second logic circuit performing logical operation between the signal passed through the first logic circuit and an output signal of the first latch circuit, and inputting a result of the logical operation to the second latch circuit.
A semiconductor device comprising:
- a memory cell;
- an input selection circuit which receives input of a first control signal, a second control signal, and a data for a scan test, selects the data for a scan test when the first control signal is activated, and selects the second control signal when the first control signal is not activated;
- a first latch circuit to which a data to be written to the memory cell is input;
- a second latch circuit provided at a post stage of the first latch circuit;
- a third latch circuit to which the data for a scan test or the second control signal selected by the input selection circuit is input;
- a first logic circuit making an output signal of the first latch circuit pass when the first control signal is not activated;
- and
- a second logic circuit performing logical operation between the signal passed through the first logic circuit and an output signal of the third latch circuit, and inputting a result of the logical operation to the second latch circuit.
Dependencies are inferred from the claim text.