US 2019/0293715 A1 · EXTRACTING DEBUG INFORMATION FROM FPGAS IN MULTI-TENANT ENVIRONMENTS

Abstract

Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.

Claims21

Dependent claims

A system, comprising:

a computing host comprising one or more processors configured to execute a supervisor process at a first privilege level and two or more user processes at a second privilege level that is lesser than the first privilege level;
and
a single field programmable gate array (FPGA) configured into a plurality of logic device portions, the portions comprising:
a host logic partition accessible only to the supervisor process executing on the computing host, wherein the first privilege level allows the supervisor process to access the host logic partition,
two or more communication lanes, each of the communication lanes being configured to communicate with a respective one of the user processes, and
two or more accelerator partitions, each of the accelerator partitions being configured to include a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and to send debug data indicating values of the logic signals to a respective one of the user processes via its associated one of the communication lanes, wherein the second privilege level allows each user process to access the respective accelerator partition and restricts access to the host logic partition.

3 more elements

A method, comprising:

programming a first portion of a programmable logic device to provide a circuit comprising an application circuit and a debug circuit, the application circuit being configured to generate and send data to application processes executed by a host computer, the debug circuit being coupled to the application circuit and being configured to capture debug data generated by exercising the application circuit;
and
programming a host portion of the programmable logic device to provide an interface to a host computer, the interface being configured to transmit the debug data to, and/or receive debug data from, the debug circuit to the host computer, the host portion of the programmable logic device being accessible to higher privilege level processes executing on the host computer than the application processes, the host portion being not accessible to the application processes executing on the host computer.

Dependencies are inferred from the claim text.

Extracting debug information from fpgas in multi-tenant environments

Life of this patent

Extracting debug information from fpgas in multi-tenant environments

Life of this patent

Abstract

Claims21