Wafer burn-in test circuit and semiconductor memory including the same
AssigneeSK hynix Inc.
InventorYoung Jae CHOI
Life of this patent
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Abstract
A wafer burn-in test circuit may be provided. The wafer burn-in test circuit may include a timing correction unit configured to generate a plurality of timing-compensated input signals by synchronizing a plurality of pulse signals generated according to a plurality of input signals with an input signal among the plurality of input signals. The wafer burn-in test circuit may include a wafer burn-in signal decoding unit configured to generate a plurality of decoding signals by decoding the plurality of timing-compensated input signals and output the plurality of decoding signals as a plurality of wafer burn-in signals by latching the plurality of decoding signals.
Claims11
A semiconductor memory comprising:
- an input and output (I/O) pad unit;
- a memory block including a plurality of unit memory blocks and an I/O circuit configured to perform a data I/O operation between the I/O pad unit and the plurality of unit memory blocks;
- and
- a wafer burin-in control unit configured to receive a portion of an address signal input through the I/O pad unit as a plurality of input signals and generate a plurality of wafer burn-in signals according to a plurality of timing-compensated input signals generated by arranging the plurality of input signals in conformity with an input signal having a latest transition timing among the plurality of input signals.
Dependencies are inferred from the claim text.