Supervisory circuit, supervisory system, motor control system

A supervisory system comprising:

• a processing circuitry configured to sequentially execute a plurality of sets of program processing, have the plurality of sets of program processing interrupted by signal processing signals outputted from a plurality of signal processing circuits, and output the plurality of sets of interrupted program processing as a register write signal;
• and
• a supervisory circuit including
• a clear code detection circuit configured to receive the register write signal and select one of the plurality of sets of interrupted program processing as a particular clear code,
• a trigger determination circuit configured to receive the signal processing signals outputted from the signal processing circuits as trigger signals, receive the particular clear code, determine whether processing operations by the signal processing circuits and the particular clear code are executed in a predetermined order, and output an interrupt signal when detecting a trigger signal out of setting, and
• a trigger table having trigger-specific tables corresponding to the respective signal processing circuits and a register-specific table corresponding to the particular clear code, the trigger table being to read a trigger setting to occur next based on a trigger determined as being correct by the trigger determination circuit, and output a table read signal to the trigger determination circuit.

A motor control system comprising:

• an AD converter configured to detect a current flowing through a motor;
• a co-processor configured to receive a current detection signal detected by the AD converter and execute phase transformation, coordinate transformation, reverse coordinate transformation, and generation of an PWM signal;
• a CPU configured to receive coordinate information outputted from the co-processor as a result of the coordinate transformation, execute speed control and current control of the motor, and output motor voltage information to the co-processor;
• and
• a supervisory system configured to receive the current detection signal outputted from the AD converter as a first trigger signal, receive the coordinate information and the PWM signal outputted from the co-processor as second trigger signals, receive the motor voltage information outputted from the CPU as a third trigger signal, determine whether the first trigger signal, the second trigger signals, and the third trigger signal are executed in a predetermined order, and output an interrupt signal when detecting a trigger signal out of setting.