# US 2019/0246166 A1 · Method and System for Implementing Media Stream Synchronization

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- Number: US 2019/0246166 A1
- Document ID: US20190246166A1
- Status: Published application
- Kind: A1
- Application number: 16/390,338
- Filed: 2019-04-22
- Published: 2019-08-08
- Earliest claimed: 2016-12-02
- Assignees: CenturyLink Intellectual Property LLC
- Applicants: CenturyLink Intellectual Property LLC
- Inventors: Michael D. Sprenger; Zubin Ingah
- Web page: https://patentgrep.com/patent/US20190246166A1

## CPC

- H04N 21/4305: {Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets (arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083)}
- H04N 21/44004: {involving video buffer management, e.g. video decoder buffer or video display buffer}
- H04N 21/44008: {involving operations for analysing video streams, e.g. detecting features or characteristics in the video stream (arrangements characterised by components specially adapted for monitoring, identification or recognition of video in broadcast systems H04H60/59)}
- H04N 21/4424: {Monitoring of the internal components or processes of the client device, e.g. CPU or memory load, processing speed, timer, counter or percentage of the hard disk space used (error monitoring in general G06F11/30; arrangements for monitoring conditions of receiving stations in broadcast systems H04H60/32; diagnosis, testing or measuring for television receivers H04N17/04)}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

Novel tools and techniques are provided for implementing media content streaming or playback, and, more particularly, for implementing media stream synchronization. In some embodiments, a synchronization system might receive a first signal that is output from a first device, which receives an original video signal from a video source and outputs a first video signal. The synchronization system might analyze the first signal to determine a first frame buffer delay, generate a delay adjustment signal based on such determination, and send the delay adjustment signal to a frame buffer delay device. The frame buffer delay device and the first device might concurrently receive the original video signal from the video source. The first delay adjustment signal causes the frame buffer delay device to apply the first frame buffer delay to the original video signal to produce a second video signal that is synchronized with the first video signal.

## Claims

### Claim 1

A method, comprising:
synchronizing, with a synchronization system, a first video signal with a second video signal that is output from a frame buffer delay device, by generating a first delay adjustment signal that causes the frame buffer delay device to apply a first frame buffer delay to an original video signal that is received by the frame buffer delay device to produce the second video signal.

### Claim 2 (depends on 1)

The method of claim 1, wherein the synchronization system comprises a timing pattern generator and an analyzer, wherein the method further comprises:
switching, using a switch, input to a first device from the video source to the timing pattern generator, wherein the synchronization system receives the first video signal from the first device;
generating, with the timing pattern generator, a first timing pattern;
sending, with the timing pattern generator, the first timing pattern to the first device via the switch, wherein synchronizing the first video signal with the second video signal comprises:
receiving, with the analyzer, a second timing pattern that is output from the first device;
analyzing, with the analyzer, the second timing pattern to determine the first frame buffer delay; and
generating, with the analyzer, the first delay adjustment signal based on the determined first frame buffer delay; and
switching, using the switch, input from the timing pattern generator to the video source, wherein synchronizing the first video signal with the second video signal further comprises sending, with the analyzer, the first delay adjustment signal to the frame buffer delay device.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first timing pattern comprises a first anchor frame pattern of a plurality of anchor frame patterns, each of the plurality of anchor frame patterns being different from each other of the plurality of anchor frame patterns, wherein the first anchor frame pattern of the plurality of anchor frame patterns is encoded on a first frame of the original video signal and a second anchor frame pattern of the plurality of anchor frame patterns is encoded on a second frame of the original video signal, wherein the first frame and the second frame are separated by a predetermined number of frames of the original video signal, with intermediate frame patterns being encoded on intermediate frames of the original video signal between the first frame and the second frame, wherein each intermediate frame pattern is the same as the first anchor frame pattern, wherein analyzing the second timing pattern to determine the first frame buffer delay comprises:
initiating, with the analyzer, a counter when a first anchor frame of the plurality of anchor frame patterns is sent to the first device;
stopping, with the analyzer, the counter when the second timing pattern is received from the output of the first device;
analyzing, with the analyzer, the second timing pattern to identify a third anchor frame of the plurality of anchor frame patterns; and
determining, with the analyzer, the first frame buffer delay, based on a value of the counter when stopped, with respect to the third anchor frame.

### Claim 4 (depends on 3)

The method of claim 3, wherein sending the first anchor frame to the first device comprises encoding the first anchor frame on a frame of the original video signal.

### Claim 5 (depends on 3)

The method of claim 3, wherein the counter comprises a clock.

### Claim 6 (depends on 3)

The method of claim 3, wherein each of the first anchor frame and the second anchor frame comprises timing information.

### Claim 7 (depends on 2)

The method of claim 2, wherein the first timing pattern and the second timing pattern are the same pattern, wherein the first timing pattern and the second timing pattern are encoded on a first frame and a second frame, respectively, of the original video signal, wherein no timing patterns are encoded on each intermediate frame of a plurality of intermediate frames between the first frame and the second frame, wherein the plurality of intermediate frames between the first frame and the second frame comprises predetermined number of intermediate frames, wherein analyzing the second timing pattern to determine the first frame buffer delay comprises:
initiating, with the analyzer, a counter when the first timing pattern is sent to the first device;
stopping, with the analyzer, the counter when the second timing pattern is received from the output of the first device; and
determining, with the analyzer, the first frame buffer delay, based on a value of the counter when stopped and based on the predetermined number of intermediate frames between the first frame and the second frame.

### Claim 8 (depends on 7)

The method of claim 7, wherein sending the first timing pattern to the first device via the switch comprises encoding, with the timing pattern generator, the first timing pattern on the first frame of the original video signal.

### Claim 9 (depends on 2)

The method of claim 2, wherein the timing pattern generator and the analyzer are part of an integrated timing pattern generator-analyzer system.

### Claim 10 (depends on 1)

The method of claim 1, wherein the synchronization system comprises a frame comparator, wherein the method further comprises:
receiving, with the frame comparator, the second video signal that is produced by the frame buffer delay device, wherein synchronizing the first video signal with the second video signal comprises:
receiving, with the frame comparator, the first video signal that is output from a first device, wherein the synchronization system receives the first video signal from the first device;
analyzing, with the frame comparator, the received first video signal and the received second video signal to determine a second frame buffer delay;
generating, with the frame comparator, a second delay adjustment signal based on the determined second frame buffer delay; and
sending, with the frame comparator, the second delay adjustment signal to the frame buffer delay device to produce the second video signal;
determining, with the frame comparator, whether the first video signal and the second video signal match to within a predetermined minimal difference; and
based on a determination that a difference between the received first video signal and the received second video signal exceeds the predetermined minimal difference, repeating the processes of:
generating, with the frame comparator, the second delay adjustment signal based on the second frame buffer delay;
sending, with the frame comparator, the second delay adjustment signal to the frame buffer delay device, the second delay adjustment signal causing the frame buffer delay device to apply the second frame buffer delay to the received original video signal to produce the second video signal;
receiving, with the frame comparator, the first video signal;
receiving, with the frame comparator, the second video signal;
analyzing, with the frame comparator, the received first video signal and the received second video signal; and
determining, with the frame comparator, whether the received first video signal and the received second video signal match to within the predetermined minimal difference.

### Claim 11 (depends on 10)

The method of claim 10, wherein determining whether the first video signal and the second video signal match to within the predetermined minimal difference comprises:
computing, with the frame comparator, a difference signal between the first video signal and the second video signal; and
analyzing, with the frame comparator, the difference signal with respect to the predetermined minimal difference.

### Claim 12 (depends on 10)

The method of claim 10, wherein determining whether the first video signal and the second video signal match to within the predetermined minimal difference comprises utilizing one of peak signal-to-noise ratio (“PSNR”) technique or root mean square (“RMS”) technique.

### Claim 13 (depends on 1)

The method of claim 1, wherein the second video signal is synchronized with the first video signal to within a predetermined threshold amount.

### Claim 14 (depends on 1)

The method of claim 1, further comprising:
comparing, with a computing system, the first video signal and the second video signal in real-time, on a frame-by-frame basis.

### Claim 15 (depends on 1)

The method of claim 1, wherein the synchronization system receives the first video signal from a first device, wherein the first device comprises one of a video encoder, a video decoder, a video encoder/decoder system, a video transcoder, a video storage and replay system, a video transport system, or a video broadcast system.

### Claim 16

A synchronization system, comprising:
at least one processor; and
a non-transitory computer readable medium communicatively coupled to the at least one processor, the non-transitory computer readable medium having stored thereon computer software comprising a set of instructions that, when executed by the at least one processor, causes the synchronization system to:
synchronize a first video signal with a second video signal that is output from a frame buffer delay device, by generating a first delay adjustment signal that causes the frame buffer delay device to apply a first frame buffer delay to an original video signal that is received by the frame buffer delay device to produce the second video signal.

### Claim 17 (depends on 16)

The synchronization system of claim 16, further comprising a timing pattern generator, an analyzer, and a switch, wherein the first signal comprises a second timing pattern, wherein the set of instructions, when executed by the at least one processor, further causes the synchronization system to:
switch, using the switch, input to a first device from the video source to the timing pattern generator, wherein the synchronization system receives the first video signal from the first device;
generate, with the timing pattern generator, a first timing pattern;
send the first timing pattern to the first device via the switch, wherein synchronizing the first video signal with the second video signal comprises:
receiving, with the analyzer, the second timing pattern that is output from the first device;
analyzing, with the analyzer, the second timing pattern to determine the first frame buffer delay; and
generating, with the analyzer, the first delay adjustment signal based on the determined first frame buffer delay; and
switch, using the switch, input from the timing pattern generator to the video source, wherein synchronizing the first video signal with the second video signal comprises sending, with the analyzer, the first delay adjustment signal to the frame buffer delay device.

### Claim 18 (depends on 16)

The synchronization system of claim 16, further comprising a frame comparator, wherein the set of instructions, when executed by the at least one processor, further causes the synchronization system to:
receive, with the frame comparator, the second video signal that is produced by the frame buffer delay device, wherein synchronizing the first video signal with the second video signal comprises:
receiving, with the frame comparator, the first video signal that is output from a first device, wherein the synchronization system receives the first video signal from the first device;
analyzing, with the frame comparator, the received first video signal and the received second video signal to determine a second frame buffer delay;
generating, with the frame comparator, a second delay adjustment signal based on the determined second frame buffer delay; and
sending, with the frame comparator, the second delay adjustment signal to the frame buffer delay device to produce the second video signal;
determine, with the frame comparator, whether the first video signal and the second video signal match to within a predetermined minimal difference; and
based on a determination that a difference between the received first video signal and the received second video signal exceeds the predetermined minimal difference, causing the synchronization system to repeat:
generating, with the frame comparator, the second delay adjustment signal based on the second frame buffer delay;
sending, with the frame comparator, the second delay adjustment signal to the frame buffer delay device, the second delay adjustment signal causing the frame buffer delay device to apply the second frame buffer delay to the received original video signal to produce the second video signal;
receiving, with the frame comparator, the first video signal;
receiving, with the frame comparator, the second video signal;
analyzing, with the frame comparator, the received first video signal and the received second video signal; and
determining, with the frame comparator, whether the received first video signal and the received second video signal match to within the predetermined minimal difference.

### Claim 19 (depends on 16)

The synchronization system of claim 16, wherein the second video signal is synchronized with the first video signal to within a predetermined threshold amount.

### Claim 20 (depends on 1)

The synchronization system of claim 1, wherein the synchronization system receives the first video signal from a first device, wherein the first device comprises one of a video encoder, a video decoder, a video encoder/decoder system, a video transcoder, a video storage and replay system, a video transport system, or a video broadcast system.