# US 2019/0245545 A1 · Device and method for controllably delaying electrical signals > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0245545 A1 - Document ID: US20190245545A1 - Status: Published application - Kind: A1 - Application number: 16/247,289 - Filed: 2019-01-14 - Published: 2019-08-08 - Earliest claimed: 2016-07-14 - Assignees: Silicon Line GmbH - Applicants: Silicon Line GmbH - Inventors: Thomas BLON - Web page: https://patentgrep.com/patent/US20190245545A1 ## CPC - H03L 7/0998: {using phase interpolation} - H03K 3/03: Astable circuits - H03K 3/0322: {with differential cells} - H03K 5/13: Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals - H03K 5/151: with two complementary outputs - H03L 7/0805: {the loop being adapted to provide an additional control signal for use outside the loop} - H03L 7/0812: {and where no voltage or current controlled oscillator is used} - H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) - H03L 7/0995: {the oscillator comprising a ring oscillator} - H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract In order to prevent or at least reduce parasitic capacitive loads at a device (200) for controllably delaying an electrical signal, the device comprising a first signal transfer path (207) between a signal input (201) and a signal output (204), the first signal transfer path (207) comprising a first signal transfer stage (208) with a first differential pair (209) and a common, adjustable first quiescent current source (212), a second signal transfer path (213) between the signal input (201) and the signal output (204), the second signal transfer path (213) comprising a second signal transfer stage (214) with a second differential pair (215) and a common, adjustable second quiescent current source (218), and an internal delay stage (219), arranged between the signal input (201) and the second signal transfer stage (214) and having a third differential pair (220) and a common, adjustable third quiescent current source (223), and a signal combination stage (224) for additively superimposing the electrical signal transferred via the first signal transfer path (207) on to the electrical signal transferred via the second signal transfer path (213), at least one current modulation stage (235, 236) for adjusting the quiescent current of at least one of the first and/or second and/or third quiescent current source (212, 218, 223) is proposed. A corresponding method for controlling the delay of an electrical signal and for said delaying the electrical signal is also proposed. ## Claims ### Claim 1 A device for controllably delaying an electrical signal, the device comprising a first signal transfer path between a signal input and a signal output, the first signal transfer path comprising a first signal transfer stage with a first differential pair and a common, adjustable first quiescent current source, a second signal transfer path between the signal input and the signal output, the second signal transfer path comprising a second signal transfer stage with a second differential pair and a common, adjustable second quiescent current source, and an internal delay stage, arranged between the signal input and the second signal transfer stage and having a third differential pair and a common, adjustable third quiescent current source, and a signal combination stage for additively superimposing the electrical signal transferred via the first signal transfer path on to the electrical signal transferred via the second signal transfer path, further comprising at least one current modulation stage for adjusting the quiescent current of at least one of the first or second or third quiescent current source. ### Claim 2 (depends on 1) The device according to claim 1, wherein the first differential pair comprises at least two emitter- or source-coupled transistors. ### Claim 3 (depends on 1) The device according to claim 1, wherein the second differential pair comprises at least two emitter- or source-coupled transistors. ### Claim 4 (depends on 1) The device according to claim 1, wherein the third differential pair comprises at least two emitter- or source-coupled transistors. ### Claim 5 (depends on 1) The device according to claim 1, further comprising a first current modulation stage for adjusting the quiescent current of the first quiescent current source and a second current modulation stage for adjusting the quiescent current of the third quiescent current source. ### Claim 6 (depends on 1) The device according to claim 1, further comprising a first current modulation stage for adjusting the quiescent current of the first quiescent current source and a third current modulation stage for adjusting the quiescent current of the second quiescent current source. ### Claim 7 (depends on 1) The device according to claim 1, wherein the first or second or third current modulation stage is designed to supply and feed a respective additional current into the quiescent current setting of the first or second or third quiescent current source. ### Claim 8 (depends on 1) The device according to claim 1, wherein the first or second or third current modulation stage is respectively provided with a first difference stage and an adjustable first current modulation quiescent current source common to the first difference stage, and with a second difference stage and an adjustable second current modulation quiescent current source common to the second difference stage, wherein the first difference stage is providable with, as a first control signal, a discretized signal for frequency increase and the second difference stage is providable with, as a second control signal, a discretized signal for frequency reduction and the first and the second current modulation quiescent current source of each current modulation stage are commonly adjustable. ### Claim 9 (depends on 8) The device according to claim 8, wherein the first difference stage comprises a first current modulation difference pair. ### Claim 10 (depends on 8) The device according to claim 8, wherein the second difference stage comprises a second current modulation difference pair. ### Claim 11 (depends on 8) The device according to claim 8, wherein the first difference stage comprises at least two emitter- or source-coupled transistors. ### Claim 12 (depends on 8) The device according to claim 8, wherein the second difference stage comprises at least two emitter- or source-coupled transistors. ### Claim 13 (depends on 8) The device according to claim 8, wherein the first current modulation quiescent current source comprises at least one fourth or sixth quiescent current source or the second current modulation quiescent current source comprises at least one fifth or seventh quiescent current source. ### Claim 14 (depends on 1) The device according to claim 1, wherein in the first or second or third current modulation stage, respectively, the first and the second current modulation quiescent current source are designed for supplying and feeding the respective additional current, controlled by the first and second control signal, into a quiescent current setting of the first or second or third quiescent current source, respectively. ### Claim 15 (depends on 1) The device according to claim 1, further comprising a first supply voltage potential at a first supply voltage connection, and a second supply voltage potential at a second supply voltage connection. ### Claim 16 (depends on 15) The device according to claim 15, wherein the second supply voltage potential is ground potential. ### Claim 17 (depends on 15) The device according to claim 15, wherein the first supply voltage potential is positive compared to the second supply voltage potential. ### Claim 18 (depends on 1) An oscillator ring, comprising at least one device according to claim 1. ### Claim 19 (depends on 1) A method for controlling the delay of an electrical signal and for said delaying the electrical signal by at least one device according to claim 1, wherein the first or second or third current modulation stage is respectively provided with, as a first control signal, a discretized signal for frequency increase, or as a second control signal, a discretized signal for frequency reduction, wherein, controlled by the first or second control signal, in the first or second or third current modulation stage a respective additional current is generated, and wherein the respective additional current of the first or second or third current modulation stage is fed into a quiescent current setting of the first or second or third quiescent current source for adjusting the quiescent current of at least one of the first or second or third quiescent current source. ### Claim 20 (depends on 1) A use of at least one device according to claim 1 in the clock and data recovery by at least one digital phase detector wherein from the at least one digital phase detector a discretized signal for frequency increase is supplied as a first control signal or a discretized signal for frequency reduction is supplied as a second control signal.