# US 2019/0245487 A1 · Logic control circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0245487 A1 - Document ID: US20190245487A1 - Status: Published application - Kind: A1 - Application number: 15/887,609 - Filed: 2018-02-02 - Published: 2019-08-08 - Earliest claimed: 2018-02-02 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Jaw-Ming DING - Web page: https://patentgrep.com/patent/US20190245487A1 ## CPC - H03F 1/0205: {in transistor amplifiers} - H03F 3/19: with semiconductor devices only - H03F 3/24: of transmitter output stages - H03F 3/245: {with semiconductor devices only} - H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal - H03F 2200/451: the amplifier being a radio frequency amplifier - H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical - H03F: AMPLIFIERS - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The present disclosure relates to a logic control circuit including a first inverter and a voltage limiter. The first inverter is connected to a first input voltage. The first inverter includes a first transistor having a first terminal and a second terminal. The second terminal of the first transistor is connected to a ground. The voltage limiter includes a second transistor. The second transistor has a gate connected to a ground, a source connected to the first terminal of the first transistor and a drain connected to a second input voltage. ## Claims ### Claim 1 A logic control circuit comprising: a first inverter connected to a first input voltage, the first inverter comprising a first transistor comprising a first terminal and a second terminal, the second terminal of the first transistor connected to ground; and a voltage limiter comprising a second transistor, the second transistor comprising a gate connected to ground, a source connected to the first terminal of the first transistor and a drain connected to a second input voltage. ### Claim 2 (depends on 1) The logic control circuit of claim 1, wherein the first terminal of the first transistor is a gate and the second terminal of the first transistor is a source. ### Claim 3 (depends on 1) The logic control circuit of claim 1, wherein the first transistor is a bipolar transistor, and the first terminal of the first transistor is a base and the second terminal of the first transistor is an emitter. ### Claim 4 (depends on 3) The logic control circuit of claim 3, wherein the voltage limiter further comprises a third transistor between the second transistor and the second input voltage, and the third transistor comprises a gate connected to ground, a source connected to the drain of the second transistor and a drain connected to the second input voltage. ### Claim 5 (depends on 3) The logic control circuit of claim 3, wherein the first transistor comprises a third terminal; the first inverter further comprises a current limiter, the current limiter comprising a third transistor and a fourth transistor; an emitter of the third transistor is connected to the third terminal of the first transistor and a gate of the fourth transistor; and a collector and a base of the third transistor are connected to a source of the fourth transistor. ### Claim 6 (depends on 5) The logic control circuit of claim 5, wherein the current limiter further comprises a fifth transistor; a source of the fifth transistor is connected to a drain of the fourth transistor; a gate of the fifth transistor is connected to the gate of the fourth transistor; and a drain of the fifth transistor is connected to the first input voltage. ### Claim 7 (depends on 3) The logic control circuit of claim 3, further comprising a second inverter, the second inverter comprising a third transistor, wherein a base of the third transistor is connected to a collector of the first transistor of the first inverter. ### Claim 8 (depends on 7) The logic control circuit of claim 7, wherein the second inverter further comprises a current limiter, the current limiter comprising a fourth transistor and a fifth transistor; an emitter of the fourth transistor is connected to a collector of the third transistor and a gate of the fifth transistor; and a collector and a base of the fourth transistor are connected to a source of the fifth transistor. ### Claim 9 (depends on 8) The logic control circuit of claim 8, wherein the current limiter further comprises a sixth transistor; a source of the sixth transistor is connected to a drain of the fifth transistor; a gate of the sixth transistor is connected to the gate of the fifth transistor; and a drain of the sixth transistor is connected to the first input voltage. ### Claim 10 (depends on 1) The logic control circuit of claim 1, wherein the first transistor is a heterojunction bipolar transistor (HBT). ### Claim 11 (depends on 1) The logic control circuit of claim 1, wherein the first transistor is a pseudomorphic high-electron mobility transistor (pHEMT). ### Claim 12 A power amplifier module comprising: a logic control circuit comprising: a first inverter connected to a first input voltage, the first inverter comprising a first transistor comprising a first terminal and a second terminal, the second terminal of the first transistor connected to ground; and a voltage limiter comprising a second transistor, the second transistor comprising a gate connected to ground, a source connected to the first terminal of the first transistor and a drain connected to a second input voltage; and an amplifier circuit configured to receive a signal from the logic control circuit. ### Claim 13 (depends on 12) The power amplifier module of claim 12, wherein the first terminal of the first transistor is a gate and the second terminal of the first transistor is a source. ### Claim 14 (depends on 12) The power amplifier module of claim 12, wherein the first transistor is a bipolar transistor, and the first terminal of the first transistor is a base and the second terminal of the first transistor is an emitter. ### Claim 15 (depends on 12) The power amplifier module of claim 12, wherein the first transistor comprises a third terminal; the first inverter further comprises a current limiter, the current limiter comprising a third transistor and a fourth transistor; an emitter of the third transistor is connected to the third terminal of the first transistor and a gate of the fourth transistor; and a collector and a base of the third transistor are connected to a source of the fourth transistor. ### Claim 16 (depends on 15) The power amplifier module of claim 15, wherein the current limiter further comprises a fifth transistor; a source of the fifth transistor is connected to a drain of the fourth transistor; a gate of the fifth transistor is connected to the gate of the fourth transistor; and a drain of the fifth transistor is connected to the first input voltage. ### Claim 17 A mobile device comprising: a case; a logic control circuit disposed within the case, the logic control circuit comprising: a first inverter connected to a first input voltage, the first inverter comprising a first transistor comprising a first terminal and a second terminal, the second terminal of the first transistor connected to ground; and a voltage limiter comprising a second transistor, the second transistor comprising a gate connected to ground, a source connected to the first terminal of the first transistor and a drain connected to a second input voltage; and an amplifier circuit disposed within the case and configured to receive a signal from the logic control circuit. ### Claim 18 (depends on 17) The mobile device of claim 17, wherein the first terminal of the first transistor is a gate and the second terminal of the first transistor is a source. ### Claim 19 (depends on 17) The mobile device of claim 17, wherein the first transistor is a bipolar transistor, and the first terminal of the first transistor is a base and the second terminal of the first transistor is an emitter. ### Claim 20 (depends on 17) The mobile device of claim 17, wherein the first transistor comprises a third terminal; the first inverter further comprises a current limiter, the current limiter comprising a third transistor and a fourth transistor; an emitter of the third transistor is connected to the third terminal of the first transistor and a gate of the fourth transistor; and a collector and a base of the third transistor are connected to a source of the fourth transistor. ### Claim 21 (depends on 20) The mobile device of claim 20, wherein the current limiter further comprises a fifth transistor; a source of the fifth transistor is connected to a drain of the fourth transistor; a gate of the fifth transistor is connected to the gate of the fourth transistor; and a drain of the fifth transistor is connected to the first input voltage.