# US 2019/0245437 A1 · Voltage charge pump with segmented boost capacitors

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- Number: US 2019/0245437 A1
- Document ID: US20190245437A1
- Status: Published application
- Kind: A1
- Application number: 16/387,808
- Filed: 2019-04-18
- Published: 2019-08-08
- Earliest claimed: 2015-03-16
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Christopher P. MILLER
- Web page: https://patentgrep.com/patent/US20190245437A1

## CPC

- H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps}
- G05F 5/00: Systems for regulating electric variables by detecting deviations in the electric input to the system and thereby controlling a device within the system to obtain a regulated output
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

## Abstract

A voltage charge pump circuit with boost capacitor segments and boost delay chain structures are provided. The voltage charge pump circuit comprising a plurality of boost capacitor segments each of which is individually controlled by a respective signal line of a boost delay chain structure.

## Claims

### Claim 1

A method comprising enabling of individual boost capacitor segments coordinated with delays, and charging an output device by a boost device in each of the individual boost capacitor segments,
wherein a first line of signal lines of a boost delay structure comprises a NAND gate in series with a first inverter, and
subsequent signal lines of the signal lines of the boost delay structure comprise a pair of inverters in series with a single input and a second NAND gate in series with a second inverter for corresponding boost capacitor segments of the boost delay structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein the individual boost capacitor segments are individually controlled by a respective signal line of the boost delay structure.

### Claim 3 (depends on 2)

The method of claim 2, further comprising controlling, individually, boost timing of each of the individual boost capacitor segments during a boost phase.

### Claim 4 (depends on 3)

The method of claim 3, further comprising delaying an input boost signal to a subsequent boost capacitor segment.

### Claim 5 (depends on 4)

The method of claim 4, wherein the delayed input boost signal fires each boost capacitor segment at a different time.

### Claim 6 (depends on 2)

The method of claim 2, further comprising providing enable signals for enabling each individual signal line such that, upon activation of an enable signal, a respective one of the individual boost capacitor segments are individually controlled.

### Claim 7 (depends on 1)

The method of claim 1, wherein the individual boost capacitor segments are driven separately to limit over voltage of a boosted node.

### Claim 8 (depends on 1)

The method of claim 1, further comprising coordinating timing control of the individual of boost capacitor segments with digital delays.

### Claim 9 (depends on 1)

The method of claim 1, further comprising distributing boost charge of the individual boost capacitor segments over time to control pump output current.

### Claim 10 (depends on 1)

The method of claim 1, wherein the boost device in each of the individual boost capacitor segments comprises a boost drive transistor.

### Claim 11 (depends on 10)

The method of claim 10, wherein the boost drive transistor is a NFET.

### Claim 12 (depends on 1)

The method of claim 1, wherein the individual boost capacitor segments are chained together by a boost delay chain which includes the pair of inventors in series.

### Claim 13 (depends on 1)

The method of claim 1, wherein the second NAND gate includes an input which is electrically connected to an enable signal.

### Claim 14 (depends on 13)

The method of claim 13, further comprising activating the enable signal using load sensing.

### Claim 15 (depends on 14)

The method of claim 14, wherein the load sensing is performed by a comparator.