# US 2019/0245142 A1 · Memory device and method of fabricating the same

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- Number: US 2019/0245142 A1
- Document ID: US20190245142A1
- Status: Published application
- Kind: A1
- Application number: 16/385,052
- Filed: 2019-04-16
- Published: 2019-08-08
- Earliest claimed: 2016-11-30
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: MASAYUKI TERAI
- Web page: https://patentgrep.com/patent/US20190245142A1

## CPC

- H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices}
- C23C 16/34: Nitrides {(C23C16/303 takes precedence)}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/82: {the switching components having a common active material layer}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/061: {Shaping switching materials}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/068: {by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/821: {Device geometry}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8418: {adapted for focusing electric field or current, e.g. tip-shaped}
- H10N 70/861: {Thermal details}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10P 14/2918: {being semiconductor metal oxides (Group IIB-VIA materials H10P14/2913)}
- H10P 14/2919: {being chalcogenide semiconducting materials not being oxides, e.g. ternary compounds}
- H10P 14/3234: {being oxide semiconducting materials (Group IIB-VIA semiconductors H10P14/3224)}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A memory cell pillar of a memory device includes a heating electrode having a base portion (leg) and a fin portion (ascender), and a selection device between a first conductive line and the heating electrode. A side surface of the selection device and a side surface of the fin portion extend along a first straight line. A method of fabricating a memory device includes forming a plurality of first insulating walls through a stack structure including a preliminary selection device layer and a preliminary electrode layer, forming a plurality of self-aligned preliminary heating electrode layers, forming a plurality of second insulating walls each between two of the plurality of first insulating walls, and forming a plurality of third insulating walls in a plurality of holes extending along a direction intersecting the plurality of first insulating walls.

## Claims

### Claim 1

A memory device comprising:
a first conductive line extending over a substrate in a first direction;
a second conductive line extending over the first conductive line in a second direction that intersects the first direction;
a memory cell pillar interposed between the first conductive line and the second conductive line; and
an insulating wall disposed upright on the substrate, the insulating wall facing a side surface of the memory cell pillar,
wherein the memory cell pillar comprises: a heating electrode layer, which has an L-shaped cross-section and comprises a base portion extending parallel to the first conductive line and a fin portion extending from an end of the base portion in a direction away from the first conductive line; and a selection device layer between the first conductive line and the heating electrode layer, and
a side surface of the selection device layer which faces the insulating wall, and a side surface of the fin portion, which faces the insulating wall, extend along a first straight line.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein the memory cell pillar further comprises an intermediate electrode layer between the selection device layer and the heating electrode layer, and
the intermediate electrode layer has a side surface facing the insulating wall and extending along the first straight line.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein the memory cell pillar further comprises an interfacial layer, which is between the selection device layer and the intermediate electrode layer and comprises a nonmetallic material, and
the interfacial layer has a side surface facing the insulating wall and extending along the first straight line.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein the memory cell pillar further comprises a bottom electrode layer between the first conductive line and the selection device layer, and
the bottom electrode layer has a side surface facing the insulating wall and extending along the first straight line.

### Claim 5 (depends on 1)

The memory device according to claim 1, wherein the memory cell pillar further comprises:
a resistive memory layer having a bottom surface, which contacts a top surface of the fin portion of the heating electrode layer, the top surface being farthest in the fin portion from the first conductive line; and
a first insulating spacer filling a reentrant corner portion and contacting the bottom surface of the resistive memory layer, the reentrant corner portion being defined by the base portion and the fin portion of the heating electrode layer, and
the area of a first bottom surface of the bottom surface of the resistive memory layer, which contacts the top surface of the fin portion, is less than the area of a second bottom surface of the bottom surface of the resistive memory layer, which contacts the first insulating spacer.

### Claim 6 (depends on 5)

The memory device according to claim 5, wherein the resistive memory layer has a side surface facing the insulating wall and extending from the fin portion toward the second conductive line in a direction that is parallel to the first straight line.

### Claim 7 (depends on 5)

The memory device according to claim 5, wherein the top surface of the fin portion and a top surface of the first insulating spacer, which faces the resistive memory layer, extend on one plane, and
the bottom surface of the resistive memory layer extends flat along the one plane.

### Claim 8 (depends on 5)

The memory device according to claim 5, wherein a first distance from the first conductive line to the top surface of the fin portion is different from a second distance from the first conductive line to a top surface of the first insulating spacer, which faces the resistive memory layer, and
the bottom surface of the resistive memory layer comprises the first bottom surface facing the top surface of the fin portion, the second bottom surface facing the first insulating spacer, and a step between the first bottom surface and the second bottom surface.

### Claim 9 (depends on 5)

The memory device according to claim 5, wherein a first distance from the first conductive line to the top surface of the fin portion is less than a second distance from the first conductive line to a top surface of the first insulating spacer, which faces the resistive memory layer.

### Claim 10 (depends on 5)

The memory device according to claim 5, wherein a first distance from the first conductive line to the top surface of the fin portion is greater than a second distance from the first conductive line to a top surface of the first insulating spacer, which faces the resistive memory layer.

### Claim 11 (depends on 5)

The memory device according to claim 5, wherein the resistive memory layer has a side surface facing the insulating wall and extending from the fin portion toward the second conductive line in a direction that is not parallel to the first straight line.

### Claim 12 (depends on 5)

The memory device according to claim 5, wherein the resistive memory layer has increasing widths in the first direction and the second direction with decreasing distance from the second conductive line.

### Claim 13 (depends on 5)

The memory device according to claim 5, wherein the resistive memory layer has a reverse truncated pyramid shape.

### Claim 14 (depends on 5)

The memory device according to claim 5, wherein the memory cell pillar further comprises a top electrode layer between the resistive memory layer and the second conductive line, and
the top electrode layer has a reverse truncated pyramid shape.

### Claim 15 (depends on 5)

The memory device according to claim 5, wherein the memory cell pillar further comprises a top electrode layer between the resistive memory layer and the second conductive line, and
the resistive memory layer and the top electrode layer form one reverse truncated pyramid shape.

### Claim 16 (depends on 5)

The memory device according to claim 5, further comprising:
a second insulating spacer between the top surface of the fin portion and the second conductive line, the second insulating spacer having a ring shape surrounding the resistive memory layer.

### Claim 17 (depends on 16)

The memory device according to claim 16, wherein the insulating wall comprises a flat side surface contacting the fin portion, and a recessed side surface, which faces the resistive memory layer and is recessed in a direction away from the resistive memory layer, and
the second insulating spacer covers the recessed side surface.

### Claim 18 (depends on 1)

The memory device according to claim 1, wherein the insulating wall has a side surface inclined with respect to a vertical line that is along a third direction perpendicular to each of the first direction and the second direction, and
the selection device layer has an decreasing width in the second direction with increasing distance from the first conductive line.