# US 2019/0245138 A1 · Top electrode cap structure for embedded memory

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- Number: US 2019/0245138 A1
- Document ID: US20190245138A1
- Status: Published application
- Kind: A1
- Application number: 16/385,271
- Filed: 2019-04-16
- Published: 2019-08-08
- Earliest claimed: 2017-08-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yao-Wen Chang; Tsung-Hsueh Yang
- Web page: https://patentgrep.com/patent/US20190245138A1

## CPC

- H10N 50/80: Constructional details
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.

## Claims

### Claim 1

A method for forming a top-electrode cap structure on a memory cell, the method comprising:
providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes;
performing an etch into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell;
forming a getter layer lining the via opening, and further over and abutting the top electrode of the memory cell; and
forming an oxygen-resistant layer over and abutting the getter layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
cleaning an uppermost surface of the top electrode to remove oxidation on the uppermost surface before the forming of the getter layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the cleaning, the forming of the getter layer, and the forming of the oxygen-resistant layer are performed in situ without moving the memory cell.

### Claim 4 (depends on 2)

The method of claim 2, wherein the cleaning is performed using an argon plasma cleaning process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the getter layer and the oxygen-resistant layer share a common element.

### Claim 6 (depends on 1)

The method of claim 1, wherein the getter layer is at least 50% getter material by weight, and wherein a getter material of the getter layer is a group IV metal.

### Claim 7 (depends on 1)

The method of claim 1, wherein the getter layer is formed of a first material that has a higher reactivity with oxygen than a second material with which the top electrode is formed.

### Claim 8 (depends on 7)

The method of claim 7, wherein the oxygen-resistant layer is formed of a third material that has a lower reactivity with oxygen than the first and second materials.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming a top electrode via (TEVA) filling the via opening over the oxygen-resistant layer, wherein the TEVA contacts the oxygen-resistant layer.

### Claim 10

A method comprising:
providing a memory cell comprising a tantalum top electrode;
depositing a dielectric layer covering the memory cell;
patterning the dielectric layer to form a top-via opening exposing the tantalum top electrode;
cleaning a top surface of the tantalum top electrode to remove oxide on the tantalum top electrode;
depositing a titanium-rich layer lining the top-via opening, wherein the titanium-rich layer comprises at least 50% titanium by mass;
depositing a titanium nitride layer lining the top-via opening over the titanium-rich layer, wherein the titanium-rich and titanium nitride layers partially fill the top-via opening; and
forming a top electrode via (TEVA) filling a remainder of the top-via opening over the titanium nitride layer.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the titanium-rich layer and the titanium nitride layer are deposited by physical vapor deposition (PVD).

### Claim 12 (depends on 10)

The method according to claim 10, wherein the patterning comprises performing an etch into the dielectric layer, wherein the etch extends below a top surface of the tantalum top electrode at sides of the tantalum top electrode and define trench segments respectively at the sides of the tantalum top electrode.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the titanium-rich layer conforms to and lines the trench segments to the sides of the tantalum top electrode.

### Claim 14 (depends on 12)

The method according to claim 12, wherein the titanium-rich layer wraps around a top corner of the tantalum top electrode and furthers lines a sidewall of the tantalum top electrode at the top corner.

### Claim 15

A method comprising:
forming a memory cell directly over a lower wire, wherein the memory cell comprises a top electrode;
forming a dielectric structure covering the memory cell;
performing a first etch into the dielectric structure to form a top-via opening exposing the top electrode;
depositing a first cap layer lining the top-via opening, wherein the first cap layer has a higher reactivity with oxygen than the top electrode;
depositing a second cap layer lining the top-via opening over the first cap layer and having a lower reactivity with oxygen than the top electrode and the first cap layer; and
forming a top electrode via (TEVA) filling a remainder of the top-via opening over the second cap layer.

### Claim 16 (depends on 15)

The method according to claim 15, wherein the first and second cap layers each has a U-shaped profile to a side of the top electrode.

### Claim 17 (depends on 15)

The method according to claim 15, wherein the depositing of the first cap layer and the depositing of the second cap layer is performed within a common process chamber, wherein the depositing of the first cap layer comprises placing the memory cell in the common process chamber, and wherein the memory cell does not leave the common process chamber until after the depositing of the second cap layer is complete.

### Claim 18 (depends on 15)

The method according to claim 15, further comprising:
depositing a via dielectric layer covering the lower wire;
patterning the via dielectric layer to form a bottom-via opening exposing a lower wire;
depositing a first conductive layer covering the via dielectric layer and filling the bottom-via opening, wherein the memory cell is formed on the first conductive layer;
forming a pair of spacer segments, wherein the memory cell is sandwiched between and border the spacer segments; and
performing a second etch into the first conductive layer using the memory cell and the spacer segments as mask, wherein the second etch forms a bottom electrode via (BEVA).

### Claim 19 (depends on 18)

The method according to claim 18, wherein the forming of the TEVA comprises:
depositing a second conductive layer covering the second cap layer and filling the remainder of the top-via opening over the second cap layer; and
performing a planarization into the second conductive layer and the first and second cap layers until a top surface of the dielectric structure is reached.

### Claim 20 (depends on 18)

The method according to claim 18, wherein the first etch extends into the spacer segments to form a recess, wherein the recess extends below a top surface of the top electrode and is lined by the first and second cap layers.