# US 2019/0245084 A1 · Transistor with Asymmetric Source and Drain Regions

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- Number: US 2019/0245084 A1
- Document ID: US20190245084A1
- Status: Published application
- Kind: A1
- Application number: 16/385,275
- Filed: 2019-04-16
- Published: 2019-08-08
- Earliest claimed: 2016-05-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: HSIEN-YUAN LIAO; CHIEN-CHIH HO; CHI-HSIEN LIN; HUA-CHOU TSENG; HO-HSIANG CHEN; RU-GUN LIU; TZU-JIN YEH; YING-TA LU
- Web page: https://patentgrep.com/patent/US20190245084A1

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/01328: {by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10P 50/264: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.

## Claims

### Claim 1

A method of forming a semiconductor structure, the method comprising:
forming an active semiconductor region in a substrate; and
forming at least three gates of a transistor over the substrate;
forming source regions and drain regions in the active semiconductor region on opposite sides of each of the at least three gates, wherein a source region corresponding to a first gate of the at least three gates and a source region corresponding to a second gate of the at least three gates coincide and have a first width, and wherein a drain region corresponding to the second gate of the at least three gates and a drain region corresponding to a third gate of the at least three gates coincide and have a second width that is not equal to the first width.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second width is greater than the first width.

### Claim 3 (depends on 1)

The method of claim 1, wherein spacings between adjacent gates in the at least three gates include a first spacing and a second spacing that is not equal to the first spacing.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first spacing defines the first width and the second spacing defines the second width, the first spacing being less than the second spacing.

### Claim 5 (depends on 3)

The method of claim 3, wherein the at least three gates define a drain-side pitch and a source-side pitch of the transistor, wherein the drain-side pitch is equal to a sum of the first width and a width of one of the at least three gates, and wherein the source-side pitch is equal to a sum of the second width and the width of the one of the at least three gates, the source-side pitch being less than the drain-side pitch.

### Claim 6 (depends on 3)

The method of claim 3, wherein the forming of the at least three gates comprises:
forming a layer of material over the substrate;
forming mandrels over the layer of material; and
forming the at least three gates by etching the layer of material, wherein a pattern of the at least three gates is defined by a pattern of the mandrels.

### Claim 7 (depends on 6)

The method of claim 6,
wherein adjacent mandrels have a pitch P, and
wherein the at least three gates define a drain-side pitch and a source-side pitch of the transistor, the source-side pitch being less than the drain-side pitch, and a sum of the drain-side pitch and source-side pitch being equal to P.

### Claim 8 (depends on 6)

The method of claim 6, wherein adjacent mandrels have a pitch P, the method further comprising:
forming a spacer layer having a thickness Ton sidewalls of the mandrels, wherein at least one of the mandrels have a mandrel width MW according to
MW
<
(
P
2
-
T
)
.

### Claim 9 (depends on 8)

The method of claim 8, wherein the thickness T of the spacer layer defines a width of the at least three gates.

### Claim 10

A method of forming a semiconductor structure comprising:
forming a layer of material over a substrate;
forming mandrels over the layer of material;
forming spacers on sidewalls of the mandrels;
removing the mandrels via an etching procedure while leaving the spacers un-removed, wherein spacings between adjacent spacers include a first spacing and a second spacing that is not equal to the first spacing;
after the removing of the mandrels, forming multiple gates in the layer of material by etching the layer of material, a pattern of the multiple gates being defined by a pattern of the spacers.

### Claim 11 (depends on 10)

The method of claim 10, wherein the mandrels have a pitch P, the spacers have a thickness T, and at least one of the mandrels have a mandrel width MW that is less than
(
P
2
-
T
)
.

### Claim 12 (depends on 10)

The method of claim 10,
wherein the multiple gates define source and drain regions of a transistor, the source and drain regions being disposed in an active semiconductor region of the substrate on opposite sides of a gate, the drain region having a first width and the source region having a second width that is less than the first width.

### Claim 13 (depends on 12)

The method of claim 12,
wherein at least one of the gates have a same width, and
wherein the multiple gates define a drain-side pitch and a source-side pitch of the transistor, the drain-side pitch being equal to a sum of the first width and the width of the gates, and the source-side pitch being equal to a sum of the second width and the width of the gates.

### Claim 14 (depends on 13)

The method of claim 13, wherein a sum of the source-side pitch and the drain-side pitch is equal to a pitch P of the mandrels.

### Claim 15

A method of forming a semiconductor structure comprising:
forming a layer over a substrate;
forming a plurality of mandrels over the layer, wherein the mandrels are spaced apart at a mandrel pitch comprising a drain side pitch and a source side pitch;
forming a spacer layer over the mandrels;
etching the spacer layer such that spacers abut both sides of each of the plurality of mandrels;
removing the plurality of mandrels via an etching procedure; and
forming a plurality of pairs of gates of a plurality of transistors in the layer by etching the layer, wherein a first distance between adjacent pairs of gates is based on the mandrel pitch, and wherein the first distance is different from a second distance between gates in each pair of gates.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
determining a desired cutoff frequency for the plurality of transistors, wherein the cutoff frequency corresponds to a frequency at which a current gain of a transistor drops to unity; and
selecting a combination of the source side pitch and the drain side pitch that will yield the desired cutoff frequency.

### Claim 17 (depends on 15)

The method of claim 15, wherein source and drain regions of the plurality of transistors are disposed in an active semiconductor region of the substrate on opposite sides of each gate in the plurality of gates, and wherein the drain region is defined by the drain side pitch and the source region is defined by the source pitch, and wherein the source side pitch is less than the drain side pitch.

### Claim 18 (depends on 15)

The method of claim 15, wherein a mandrel width is defined by
MW
<
(
P
2
-
T
)
wherein MW corresponds to the mandrel width, P corresponds to the mandrel pitch, and T corresponds to a thickness of the spacers.

### Claim 19 (depends on 15)

The method of claim 15, wherein the layer comprises polysilicon, and wherein the plurality of gates comprise polysilicon.

### Claim 20 (depends on 15)

The method of claim 15, wherein the spacers are retained during the etching procedure to remove the plurality of mandrels.