# US 2019/0245083 A1 · Close proximity and lateral resistance reduction for bottom source/drain epitaxy in vertical transistor devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0245083 A1
- Document ID: US20190245083A1
- Status: Published application
- Kind: A1
- Application number: 15/888,745
- Filed: 2018-02-05
- Published: 2019-08-08
- Earliest claimed: 2018-02-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Alexander Reznicek; Shogo Mochizuki; Jingyun Zhang; Xin Miao
- Web page: https://patentgrep.com/patent/US20190245083A1

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 50/642: {Chemical etching}
- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

## Claims

### Claim 1

A semiconductor structure comprising:
at least one semiconductor fin extending upwards from a semiconductor base of a semiconductor substrate, wherein the semiconductor base comprises an upper portion, a lower portion and a midsection, wherein the midsection has a narrower width than the lower and upper portions;
a bottom source/drain structure located on surfaces of the semiconductor substrate and surfaces of semiconductor base, wherein the bottom source/drain structure has a tip region that contacts a midsection of the semiconductor base;
a gate structure located above the bottom source/drain structure and on each side of the at least one semiconductor fin; and
a top source/drain structure located on a topmost surface of the at least one semiconductor fin.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric material layer and a gate conductor, wherein the gate dielectric material layer directly contacts sidewall surfaces of the at least one semiconductor fin.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the gate structure further comprises a work function metal layer located between the gate dielectric material layer and the gate conductor.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, further comprising a bottom spacer located between the gate structure and the bottom source/drain structure, wherein the bottom spacer contacts a lower portion of the least one semiconductor fin.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, further comprising a top spacer located on a topmost surface of the gate structure and contacting an upper portion of the least one semiconductor fin.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor substrate that lies adjacent the semiconductor base has a concave surface.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the top source/drain structure has a faceted surface.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the top source/drain structure has a diamond shape.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, further comprising a middle-of-the-line (MOL) dielectric material laterally surrounding the gate structure, the semiconductor fin and the top source/drain contact.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, further comprising a source/drain contact contacting each of the top source/drain structure and the bottom source/drain structure.

### Claim 11

A method of forming a semiconductor structure, the method comprising:
forming at least one semiconductor fin extending upwards from a semiconductor substrate, wherein a dielectric spacer is present on each sidewall surface of the at least one semiconductor fin and a hard mask is located on a topmost surface of the at least one semiconductor fin;
recessing the semiconductor substrate to provide a semiconductor pedestal beneath the dielectric spacer and the at least one semiconductor fin:
performing a self-limiting etch to convert at least the semiconductor pedestal into a semiconductor base comprises an upper portion, a lower portion and a midsection, wherein the midsection has a narrower width than the lower and upper portions;
forming a bottom source/drain structure on physically exposed surfaces of the semiconductor base and the semiconductor substrate;
removing each dielectric spacer from length-wise sidewalls of the at least one semiconductor fin;
forming a gate structure above the bottom source/drain structure and on each side of the at least one semiconductor fin;
removing the hard mask from the at least one semiconductor fin; and
forming a top source/drain structure on a topmost surface of the at least one semiconductor fin.

### Claim 12 (depends on 11)

The method of claim 11, wherein the self-limiting etch comprises a sigma etch.

### Claim 13 (depends on 11)

The method of claim 11, further comprising performing a second recessing of the semiconductor substrate after the performing of the self-limiting etch and prior to the forming of the bottom source/drain structure.

### Claim 14 (depends on 11)

The method of claim 11, further comprising forming an implant region in the semiconductor substrate after the recessing of the semiconductor substrate and prior to the performing of the self-limiting etch, wherein the implant region prevent etching of the semiconductor substrate during the self-limiting etch.

### Claim 15 (depends on 14)

The method of claim 14, further comprising performing a second recessing of the semiconductor substrate after the performing of the self-limiting etch and prior to the forming of the bottom source/drain structure, wherein the second recessing removes the implant region and a portion of the semiconductor substrate.

### Claim 16 (depends on 11)

The method of claim 11, wherein the bottom source/drain structure and the top source/drain structure are formed by an epitaxial growth process.

### Claim 17 (depends on 11)

The method of claim 11, further comprising forming a bottom spacer located on the bottom source/drain structure prior to the forming the gate structure.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming a top spacer located on a topmost surface of the gate structure prior to forming the top source/drain structure.

### Claim 19 (depends on 11)

The method of claim 11, wherein the forming the gate structure comprises forming a gate dielectric material layer and a gate conductor, wherein the gate dielectric material layer directly contacts sidewall surfaces of the at least one semiconductor fin.

### Claim 20 (depends on 19)

The method of claim 19, wherein the forming the gate structure further comprises forming a work function metal layer between the gate dielectric material layer and the gate conductor.