# US 2019/0245076 A1 · Semiconductor devices having source/drain regions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0245076 A1 - Document ID: US20190245076A1 - Status: Published application - Kind: A1 - Application number: 16/129,935 - Filed: 2018-09-13 - Published: 2019-08-08 - Earliest claimed: 2018-02-06 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Geum-jung SEONG; Bo-ra LIM; Jeong-yun LEE; Ah-reum JI - Web page: https://patentgrep.com/patent/US20190245076A1 ## CPC - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/6213: {having rounded corners} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/117: {Shapes of semiconductor bodies} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/834: {comprising FinFETs} - H10D 84/853: {comprising FinFETs} - H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a substrate having a fin active region pattern having a protruding shape, a device isolation layer pattern covering a side surface of a lower portion of the fin active region pattern, a spacer pattern covering a side surface of a portion of the fin active region pattern that protrudes from a top surface of the device isolation layer pattern, and a source/drain region in contact with a top surface of the fin active region pattern and a top surface of the spacer pattern. ## Claims ### Claim 1 A semiconductor device comprising: a substrate having a fin active region pattern having a protruding shape; a device isolation layer pattern covering a side surface of a lower portion of the fin active region pattern; a spacer pattern covering a side surface of a portion of the fin active region pattern, the portion of the fin active region pattern protruding from a top surface of the device isolation layer pattern; and a source/drain region in contact with a top surface of the fin active region pattern and a top surface of the spacer pattern. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the source/drain region comprises a lower side unit having a constant lateral width or a lateral width reducing away from the substrate in a vertical direction, and an upper side unit having a lateral width that increases and then decreases away from the lower side unit in the vertical direction. ### Claim 3 (depends on 2) The semiconductor device of claim 2, further comprising an etch stop film covering the source/drain region and the spacer pattern, wherein the etch stop film is in contact with a side surface of the lower side unit of the source/drain region. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the etch stop film is spaced apart from the fin active region pattern with the spacer pattern therebetween. ### Claim 5 (depends on 2) The semiconductor device of claim 2, wherein the lateral width of the lower side unit is greater than a lateral width of the portion of the fin active region pattern protruding from the top surface of the device isolation layer pattern. ### Claim 6 (depends on 2) The semiconductor device of claim 2, wherein a lateral width of a portion of the lower side unit in contact with the fin active region pattern and the spacer pattern is equal to a sum of a lateral width of a portion of the fin active region pattern in contact with the lower side unit and a lateral width of a portion of the spacer pattern in contact with the lower side unit. ### Claim 7 (depends on 3) The semiconductor device of claim 3, wherein a bottom surface of the lower side unit is in contact with the fin active region pattern, the spacer pattern, and the etch stop film. ### Claim 8 (depends on 2) The semiconductor device of claim 2, wherein a side surface of a portion of an uppermost end of the fin active region pattern is covered by the lower side unit, and a side surface of a remaining portion of the uppermost end of the fin active region pattern is covered by the spacer pattern. ### Claim 9 (depends on 2) The semiconductor device of claim 2, wherein an uppermost end of the spacer pattern is at a lower level than a lowermost end of the upper side unit of the source/drain region. ### Claim 10 A semiconductor device comprising: a substrate having a first fin active region pattern and a second fin active region pattern, each of which has a protruding shape; a device isolation layer pattern covering a side surface of a lower portion of each of the first fin active region pattern and the second fin active region pattern; a first source/drain region in contact with the first fin active region pattern, the first source/drain region including a first lower side unit and a first upper side unit on the first lower side unit; and a second source/drain region in contact with a top surface of the second fin active region pattern, the second source/drain region including a second lower side unit and a second upper side unit on the second lower side unit, wherein each of the first lower side unit and the second lower side unit has a constant lateral width or a lateral width reducing away from the substrate in a vertical direction, and the lateral width of the first lower side unit is greater than the lateral width of the second lower side unit. ### Claim 11 (depends on 10) The semiconductor device of claim 10, further comprising: a first spacer pattern covering a side surface of a portion of the first fin active region pattern protruding from a top surface of the device isolation layer pattern; and a second spacer pattern covering a side surface of a portion of the second fin active region pattern protruding from the top surface of the device isolation layer pattern and a side surface of the second lower side unit. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein an uppermost end of the first spacer pattern is at a higher level than an uppermost end of the second spacer pattern. ### Claim 13 (depends on 11) The semiconductor device of claim 11, further comprising an etch stop film covering the first source/drain region, the second source/drain region, the first spacer pattern, and the second spacer pattern, wherein the etch stop film is in contact with a side surface of the first lower side unit. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the etch stop film is spaced apart from the second lower side unit with the second spacer pattern therebetween. ### Claim 15 (depends on 10) The semiconductor device of claim 10, wherein a height of the first lower side unit is greater than a height of the second lower side unit. ### Claim 16 (depends on 10) The semiconductor device of claim 10, wherein an uppermost end of the first source/drain region is at a higher level than an uppermost end of the second source/drain region. ### Claim 17 A semiconductor device comprising: a substrate having a first fin active region pattern and a second fin active region pattern formed in a first region and a second region, respectively, wherein the first fin active region pattern and the second fin active region pattern are doped with impurities of different conductivity types; a device isolation layer pattern covering side surfaces of lower portions of the first fin active region pattern and the second fin active region pattern, respectively; a spacer pattern covering a side surface of a portion of the first fin active region pattern protruding from a top surface of the device isolation layer pattern and a side surface of a portion of the second fin active region pattern; a first source/drain region including a first lower side unit in contact with a top surface of the first fin active region pattern and a top surface of the spacer pattern and a first upper side unit on the first lower side unit; and a second source/drain region including a second lower side unit in contact with a top surface of the second fin active region pattern and the top surface of the spacer pattern and a second upper side unit on the second lower side unit, wherein each of the first lower side unit and the second lower side unit has a lateral width reducing away from the substrate in a vertical direction. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the first upper side unit has a polyhedral shape having facets, and at least a portion of a surface of the second upper side unit has a round shape. ### Claim 19 (depends on 17) The semiconductor device of claim 17, further comprising an etch stop film covering the first source/drain region, the second source/drain region, and the spacer pattern, wherein the etch stop film is in contact with each of a side surface of the first lower side unit and a side surface of the second lower side unit. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein the etch stop film is spaced apart from each of the first fin active region pattern and the second fin active region pattern with the spacer pattern therebetween, and an uppermost end of the spacer pattern is at a lower level than each of a lowermost end of the first upper side unit and a lowermost end of the second upper side unit.