# US 2019/0245071 A1 · Single electron transistors

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- Number: US 2019/0245071 A1
- Document ID: US20190245071A1
- Status: Published application
- Kind: A1
- Application number: 16/318,527
- Filed: 2016-09-24
- Published: 2019-08-08
- Earliest claimed: 2016-09-24
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Hubert C. George
- Web page: https://patentgrep.com/patent/US20190245071A1

## CPC

- H10D 30/402: {Single electron transistors; Coulomb blockade transistors}
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/814: {Quantum box structures}
- H10D 64/23: Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 64/311: {Gate electrodes for field-effect devices}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/82: of only field-effect components
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 95/062: {involving a dielectric removal step}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes disposed on a side face of a first insulating support and on a side face of a second insulating support, respectively; an island disposed between the first and second S/D electrodes and extending into an area between the first and second insulating supports. In some embodiments, a SET device may include: first and second S/D electrodes disposed on a substrate; an island disposed in an area between the first and second S/D electrodes; first and second portions of dielectric disposed between the island and the first and second S/D electrodes, respectively; and a third portion of dielectric disposed between the substrate and the island.

## Claims

### Claim 1

A device, comprising:
first and second insulating supports;
first and second source/drain (S/D) electrodes of a single electron transistor (SET), wherein the first S/D electrode is at a side face of the first insulating support and the second S/D electrode is at a side face of the second insulating support;
an island of the SET, between the first and second S/D electrodes and extending into an area between the first and second insulating supports; and
first and second portions of a dielectric, wherein the first portion of the dielectric is between the first S/D electrode and the island, and the second portion of the dielectric is between the second S/D electrode and the island, to provide first and second tunnel junctions (TJs), respectively.

### Claim 2 (depends on 1)

The device of claim 1, wherein a height of the island is less than a height of the first S/D electrode.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first and second S/D electrodes are on a substrate, and another portion of the dielectric is between the substrate and the island.

### Claim 4 (depends on 1)

The device of claim 1, wherein the first and second portions of the dielectric have a thickness between 0.5 and 5 nanometers.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first and second S/D electrodes have a thickness, measured from side faces of the first and second insulating supports, respectively, between 1 and 10 nanometers.

### Claim 6 (depends on 1)

The device of claim 1, further comprising:
a third insulating support; and
a gate electrode of the SET at a side face of the third insulating support.

### Claim 7 (depends on 6)

The device of claim 6, wherein the side face of the third insulating support faces the side faces of the first and second insulating supports.

### Claim 8 (depends on 6)

The device of claim 6, further comprising:
a third portion of the dielectric between the island and the gate electrode.

### Claim 9 (depends on 1)

The device of claim 1, wherein the SET is a first SET, the island is a first island, the side face of the first insulating support is a first side face of the first insulating support, the side face of the second insulating support is a first side face of the second insulating support, and the device further includes:
third and fourth S/D electrodes of a second SET, wherein the third S/D electrode is at a second side face of the first insulating support and the fourth S/D electrode is at a second side face of the second insulating support;
a second island of the second SET, between the third and fourth S/D electrodes and extending into the area between the first and second insulating supports; and
third and fourth portions of the dielectric; wherein the third portion of the dielectric is between the third S/D electrode and the second island, and the fourth portion of the dielectric is between the fourth S/D electrode and the second island.

### Claim 10 (depends on 9)

The device of claim 9, further comprising:
a third insulating support; and
a gate electrode of the first SET at a side face of the third insulating support, wherein the side face of the third insulating support faces the first side faces of the first and second insulating supports.

### Claim 11 (depends on 10)

The device of claim 10, wherein the gate electrode is a first gate electrode, the side face of the third insulating support is a first side face, and the device further includes:
a second gate electrode at a second side face of the third insulating support.

### Claim 12 (depends on 10)

The device of claim 10, further comprising:
a fourth insulating support; and
a gate electrode of the second SET device at a side face of the fourth insulating support, wherein the side face of the fourth insulating support faces the second side faces of the first and second insulating supports.

### Claim 13 (depends on 9)

The device of claim 9, wherein a third insulating support is between the first and second insulating supports, and the third insulating support is between the first and second islands.

### Claim 14 (depends on 13)

The device of claim 13, wherein a fifth portion of the dielectric is between the third insulating support and the first island, and a sixth portion of the dielectric is between the third insulating support and the second island.

### Claim 15 (depends on 1)

The device of claim 1, wherein the first and second insulating supports are materially contiguous with a third insulating support between the first and second insulating supports.

### Claim 16 (depends on 1)

The device of claim 1, wherein the side face of the first insulating support is a first side face of the first insulating support, and the device further includes: a gate electrode at a second side face of the first insulating support.

### Claim 17

A method of manufacturing a single electron transistor (SET device), comprising:
forming an insulating support;
providing a conductive material on at least one side face of the insulating support;
after providing the conductive material, providing an insulating material on the conductive material and the insulating support to form a first assembly;
forming a recess in the first assembly, wherein the recess extends into the insulating support and separates the conductive material into at least first and second separate conductive portions;
providing a dielectric on sidewalls and bottom of the recess; and
providing an island material in the recess on the dielectric.

### Claim 18

(canceled)

### Claim 19 (depends on 17)

The method of claim 17, wherein the insulating support is a first insulating support, and further comprising:
forming a second insulating support parallel to the first insulating support; and
providing a conductive material on at least one side face of the second insulating support.

### Claim at position 20

20-23. (canceled)

### Claim 24

A computing device, comprising:
a processing device including one or more single electron transistors (SETs), wherein individual ones of the SETs include:
first and second source/drain (S/D) electrodes, wherein the first S/D electrode is at a side face of a first insulating support and the second S/D electrode is at a side face of a second insulating support,
an island, between the first and second S/D electrodes and extending into an area between the first and second insulating supports, and
first and second portions of a dielectric, wherein the first portion of the dielectric is between the first S/D electrode and the island, and the second portion of the dielectric is between the second S/D electrode and the island; and
a memory device, coupled to the processing device.

### Claim 25 (depends on 24)

The computing device of claim 24, wherein the processing device includes one or more field effect transistors.