# US 2019/0245045 A1 · Group iii nitride semiconductor device and method of manufacturing group iii nitride semiconductor substrate

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- Number: US 2019/0245045 A1
- Document ID: US20190245045A1
- Status: Published application
- Kind: A1
- Application number: 16/245,003
- Filed: 2019-01-10
- Published: 2019-08-08
- Earliest claimed: 2018-02-06
- Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho
- Applicants: Kabushiki Kaisha Toyota Chuo Kenkyusho
- Inventors: Keita KATAOKA; Tetsuo NARITA
- Web page: https://patentgrep.com/patent/US20190245045A1

## CPC

- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/154: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/53: the imperfections being within the semiconductor body
- H10D 62/57: the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/143: {the built-in components being PN junction diodes}
- H10P 14/2908: {Nitrides}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a group III nitride semiconductor substrate may comprise introducing group III element vacancies to a first region of the group III nitride semiconductor substrate. The method may comprise introducing an acceptor element to a second region of the group III nitride semiconductor substrate. The second region may contact the first region at least in part. The method may comprise performing annealing to activate the acceptor element in the second region.

## Claims

### Claim 1

A method of manufacturing a group III nitride semiconductor substrate, the method comprising:
introducing group III element vacancies to a first region of the group III nitride semiconductor substrate;
introducing an acceptor element to a second region of the group III nitride semiconductor substrate, the second region contacting the first region at least in part; and
performing annealing to activate the acceptor element in the second region.

### Claim 2 (depends on 1)

The method of manufacturing a group III nitride semiconductor substrate according to claim 1, wherein
the introducing of group III element vacancies includes ion-implanting group III element ions or inert gas ions.

### Claim 3

A group III nitride semiconductor device comprising:
a first region; and
a second region,
wherein
at least a part of the first region contacts the second region,
the second region includes an acceptor element, and
a defect concentration in the first region is higher than a defect concentration in the second region.

### Claim 4 (depends on 3)

The group III nitride semiconductor device according to claim 3, wherein
the defect concentration in the second region is lower than an acceptor element concentration in the second region.

### Claim 5 (depends on 3)

The group III nitride semiconductor device according to claim 3, wherein
particles of the acceptor element are distributed in the second region according to an impurity distribution generated by ion implantation.

### Claim 6 (depends on 3)

The group III nitride semiconductor device according to claim 3, wherein
at least a part of the first region includes a group III element other than a group III element constituting the group III nitride semiconductor device, or an inert gas element.

### Claim 7 (depends on 3)

The group III nitride semiconductor device according to claim 3, further comprising:
a group III nitride semiconductor substrate including a part of the first region and a part of the second region located on a surface of the group III nitride semiconductor substrate; and
a first electrode contacting the part of the first region and the part of the second region that are located on the surface of the group III nitride semiconductor substrate.

### Claim 8 (depends on 3)

The group III nitride semiconductor device according to claim 3, further comprising:
a group III nitride semiconductor substrate including a part of the second region located on a surface of the group III nitride semiconductor substrate and the first region located inside the group III nitride semiconductor substrate; and
a first electrode contacting the part of the second region that is located on the surface of the group III nitride semiconductor substrate.

### Claim 9 (depends on 3)

The group III nitride semiconductor device according to claim 3, further comprising:
an n-type drift layer;
a body layer disposed on an upper surface of the drift layer; and
a trench gate extending from an upper surface of the body layer into the drift layer,
wherein
the first region and the second region are disposed inside the body layer, and
a distance between the second region and the trench gate is smaller than a distance between the first region and the trench gate.