# US 2019/0245035 A1 · High energy ion implantation for junction isolation in silicon carbide devices

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- Number: US 2019/0245035 A1
- Document ID: US20190245035A1
- Status: Published application
- Kind: A1
- Application number: 15/890,077
- Filed: 2018-02-06
- Published: 2019-08-08
- Earliest claimed: 2018-02-06
- Assignees: General Electric Company
- Applicants: General Electric Company
- Inventors: Reza Ghandi; David Alan Lilienfeld; Alexander Viktorovich Bolotnikov; Peter Almern Losee
- Web page: https://patentgrep.com/patent/US20190245035A1

## CPC

- H10D 62/114: {PN junction isolations}
- H10D 62/8325: {Silicon carbide}
- H10D 84/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/035: {using silicon carbide [SiC] technology}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 14/3408: {Silicon carbide}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/2042: {into crystalline silicon carbide}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).

## Claims

### Claim 1

An integrated circuit, comprising:
a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type; and
a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type, wherein the junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the depth of the junction isolation feature is between about 3 μm and about 10 μm.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the junction isolation feature has a width between about 1 μm and about 10 μm.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the junction isolation feature is formed via high-energy ion implantation performed at ion implantation energies between about 2 megaelectron volts (MeV) and about 60 MeV.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the junction isolation feature is formed via multi-energy ion implantation.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein the junction isolation feature is disposed in the SiC epitaxial layer between or around adjacent planar devices and the junction isolation feature electrically isolates the adjacent planar devices.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, wherein the adjacent planar devices comprise transistors, diodes, resistors, capacitors, or a combination thereof, and wherein the transistors comprise metal-oxide-semiconductor (MOS) transistors, complementary MOS (CMOS) transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), junction gate field-effect transistors (JFETs), insulated gate bipolar transistors (IGBTs), or a combination thereof.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein the junction isolation feature has a dopant concentration between about 1×1014 per cubic centimeters (cm−3) and about 1×1018 cm−3 of the second conductivity-type.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, wherein the junction isolation feature has a dopant concentration that is at least four times a dopant concentration of the SiC epitaxial layer.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, wherein the first conductivity-type is n-type and the junction isolation feature is doped with aluminum, boron, or both.

### Claim 11 (depends on 1)

The integrated circuit of claim 1, wherein the first conductive type is p-type and the junction isolation feature is doped with nitrogen, phosphorous, or both.

### Claim 12 (depends on 1)

The integrated circuit of claim 1, wherein the integrated circuit is part of a power conversation device of a power conversion system.

### Claim 13

A method of manufacturing a semiconductor device, comprising:
providing a silicon carbide (SiC) epitaxial layer on top of an underlying SiC layer;
fabricating features of adjacent planar devices in the SiC epitaxial layer, wherein the adjacent planar devices comprise transistors, resistors, capacitors, diodes, or a combination thereof, the SiC epitaxial layer is a first conductive type, and the underlying SiC layer is a second conductive type opposite to the first conductive type;
forming a junction isolation feature between or around the adjacent planar devices by implanting dopants in the epitaxial SiC layer via high-energy ion implantation, wherein the junction isolation feature has a depth of at least about 2 micrometers (μm) such that the junction isolation feature extends vertically through a thickness of the epitaxial SiC layer and contacts or penetrates into the underlying SiC layer; and
annealing the junction isolation feature.

### Claim 14 (depends on 13)

The method of claim 13, wherein annealing the junction isolation feature comprises annealing the junction isolation feature before, after, or at the same time as annealing the adjacent planar devices.

### Claim 15 (depends on 13)

The method of claim 13, wherein forming the junction isolation feature comprises performing the high-energy ion implantation at implantation energies between about 2 megaelectron volts (MeV) and about 60 MeV.

### Claim 16 (depends on 13)

The method of claim 13, wherein forming the junction isolation feature comprises performing multi-energy ion implantation.

### Claim 17 (depends on 13)

The method of claim 13, wherein forming the junction isolation feature comprises implanting aluminum ions, boron ions, or both, when the first conductive type is n-type.

### Claim 18 (depends on 13)

The method of claim 13, wherein forming the junction isolation feature comprises implanting nitrogen irons, phosphorous ions, or both when the first conductive type is p-type.

### Claim 19 (depends on 13)

The method of claim 13, wherein forming the junction isolation feature comprises implanting the dopants in the SiC epitaxial layer with a dopant concentration between about 1×1014 ions per cubic centimeters (ions/cm3) and about 1×1018 ions/cm3.

### Claim 20 (depends on 13)

The method of claim 13, wherein annealing the semiconductor device is performed at temperatures between about 1400 degrees Celsius (° C.) and about 2000° C. for a duration of about 10 minutes to about 60 minutes.

### Claim 21 (depends on 13)

The method of claim 13, comprising forming a bias contact on top of the junction isolation feature, wherein the bias contact electrically couples the junction isolation feature to one or more terminal contacts of the adjacent planar devices.

### Claim 22

A silicon carbide (SiC) integrated circuit comprising:
a SiC layer of a first conductive type;
a SiC epitaxial layer of a second conductive type disposed on the SiC layer, wherein the second conductive type is opposite to the first conductive type;
adjacent planar transistors, each comprises a source contact and a drain contact disposed on the SiC epitaxial layer; and
a junction isolation feature formed between or around the adjacent planar transistors, wherein the junction isolation featured is doped with ions of the first conductive type at a concentration that is between about 1×1014 ions per cubic centimeters (ions/cm3) and about 1×1018 ions/cm3, wherein the junction isolation feature has a width that is between about 1 micrometers (μm) and about 10 μm, and wherein the junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer.

### Claim 23 (depends on 22)

The SiC integrated circuit of claim 22, wherein the thickness of the SiC epitaxial layer is at least about 2 micrometers (μm).

### Claim 24 (depends on 22)

The SiC integrated circuit if claim 22, wherein the SiC integrated circuit is configured to operate at temperatures above about 250 degrees Celsius.

### Claim 25 (depends on 22)

The power conversion device of claim 22, wherein the junction isolation feature is formed via multi-energy ion implantation at implantation energies between about 2 megaelectron volts (MeV) and about 60 MeV.

### Claim 26 (depends on 22)

The power conversion device of claim 22, wherein the SiC integrated circuit is annealed at temperatures between about 1400 degrees Celsius (° C.) and about 2000° C. for a duration of about 10 minutes to about 60 minutes.