# US 2019/0245031 A1 · Low warpage high density trench capacitor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0245031 A1 - Document ID: US20190245031A1 - Status: Published application - Kind: A1 - Application number: 16/387,844 - Filed: 2019-04-18 - Published: 2019-08-08 - Earliest claimed: 2017-09-01 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Jyun-Ying Lin; Hsin-Li Cheng; Jing-Hwang Yang; Felix Ying-Kit Tsui; Chien-Li Kuo - Web page: https://patentgrep.com/patent/US20190245031A1 ## CPC - H10D 1/042: {using deposition processes to form electrode extensions} - H10B 12/0387: {Making the trench} - H10B 12/37: {the capacitor being at least partially in a trench in the substrate} - H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching} - H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors} - H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors} - H10D 1/714: {having horizontal extensions} - H10D 1/716: {having vertical extensions} - H10D 86/85: characterised by only passive components - H10P 14/416: {of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers} - H10P 50/264: {by chemical means} - H10P 50/283: {by chemical means} - H10P 50/642: {Chemical etching} - H10P 52/403: {of conductive or resistive materials} - H10P 76/2041: {Photolithographic processes} - H10P 95/062: {involving a dielectric removal step} - H10W 10/021: {of air gaps} - H10W 10/20: Air gaps - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10D 84/212: {of only capacitors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/354: {comprising polymers} - H10W 72/552: {comprising metals or metalloids, e.g. silver} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure. ## Claims ### Claim 1 A method of forming a capacitor structure, comprising: forming a two-dimensional trench array within a substrate, wherein the two-dimensional trench array has a plurality of segments defined therein, wherein the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array, and wherein each of the plurality of segments comprises an array of a plurality of recesses having a predetermined length extending along a surface of the substrate; depositing a first dielectric layer on a bottom region and sidewalls of the plurality of recesses and on the surface of the substrate; depositing a first conducting layer of a first thickness over the first dielectric layer, wherein the first thickness is substantially uniform; depositing a second dielectric layer over the first conducting layer; depositing a second conducting layer of a second thickness over the second dielectric layer, wherein the second thickness is substantially uniform; removing portions of the second conducting layer and the second dielectric layer not within the plurality of recesses; and removing portions of the first conducting layer and the first dielectric layer on the surface which are not within a local region of the plurality of recesses. ### Claim 2 (depends on 1) The method of claim 1, wherein one or more of a photolithographic etch and a chemical-mechanical polish is utilized to remove the portions of the second conducting layer and second dielectric layer. ### Claim 3 (depends on 1) The method of claim 1, wherein the second conducting layer fills a remainder of the plurality of recesses not filled by the first conducting layer while maintaining an air gap between the respective sidewalls of the plurality of recesses. ### Claim 4 (depends on 1) The method of claim 1, wherein a pattern and etch process is utilized to remove the portions of the first conducting layer and first dielectric layer. ### Claim 5 (depends on 1) The method of claim 1, wherein forming the two-dimensional trench array comprises etching a doped region of the substrate. ### Claim 6 (depends on 5) The method of claim 5, further comprising implanting ions in the substrate prior to forming the two-dimensional trench array within the substrate, therein defining the doped region of the substrate. ### Claim 7 (depends on 1) The method of claim 1, wherein one or more of the first dielectric layer and the second dielectric layer comprises an oxide/nitride/oxide composite layer. ### Claim 8 (depends on 1) The method of claim 1, wherein the first conducting layer or the second conducting layer comprises polysilicon. ### Claim 9 (depends on 1) The method of claim 1, wherein depositing the second conducting layer comprises generally filling a remainder of the plurality of recesses not filled by the first conducting layer while maintaining an air gap between the sidewalls of the respective plurality of recesses. ### Claim 10 (depends on 1) The method of claim 1, wherein the two-dimensional trench array comprises two first arrays and two second arrays, wherein each of the first arrays are diametrically opposed to one another about the center of the capacitor structure, and wherein each of the second arrays are diametrically opposed to one another about the center of the capacitor structure, wherein the two first arrays and two second arrays define a rotationally symmetric layout. ### Claim 11 A method of forming a semiconductor die, the method comprising: forming a capacitor structure, wherein forming the capacitor structure comprises: forming a two-dimensional trench array within a substrate, wherein the two-dimensional trench array has a plurality of segments defined therein, wherein the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array, and wherein each of the plurality of segments comprises an array of a plurality of recesses having a predetermined length extending along a surface of the substrate; depositing a first dielectric layer on a bottom region and sidewalls of the plurality of recesses and on the surface of the substrate; depositing a first conducting layer of a first thickness over the first dielectric layer, wherein the first thickness is substantially uniform; depositing a second dielectric layer over the first conducting layer; depositing a second conducting layer of a second thickness over the second dielectric layer, wherein the second thickness is substantially uniform; removing portions of the second conducting layer and the second dielectric layer not within the plurality of recesses; and removing portions of the first conducting layer and the first dielectric layer on the surface which are not within a local region of the plurality of recesses; and electronically coupling the capacitor structure to an integrated circuit on the semiconductor die. ### Claim 12 (depends on 11) The method of claim 11, wherein electronically coupling the capacitor structure to the integrated circuit comprises forming one or more of a wire bond, a through silicon via, or a bond pad between the capacitor structure and the integrated circuit. ### Claim 13 (depends on 12) The method of claim 12, comprising forming a plurality of capacitor structures, wherein each of the plurality of capacitor structures are electronically coupled to the integrated circuit. ### Claim 14 (depends on 11) The method of claim 11, wherein removing the portions of the second conducting layer and second dielectric layer comprises performing one or more of a photolithographic etch and a chemical-mechanical polish. ### Claim 15 (depends on 11) The method of claim 11, wherein the second conducting layer fills a remainder of the plurality of recesses not filled by the first conducting layer while maintaining an air gap between the respective sidewalls of the plurality of recesses. ### Claim 16 (depends on 11) The method of claim 11, wherein a pattern and etch process is utilized to remove the portions of the first conducting layer and first dielectric layer. ### Claim 17 (depends on 11) The method of claim 11, wherein depositing the second conducting layer comprises generally filling a remainder of the plurality of recesses not filled by the first conducting layer while maintaining an air gap between the sidewalls of the respective plurality of recesses. ### Claim 18 A method of forming a semiconductor die, the method comprising: forming a plurality of capacitor structures, wherein forming the plurality of capacitor structures comprises: etching a doped region of a substrate, thereby defining a two-dimensional trench array having a plurality of segments defined therein, wherein the plurality of segments define a pair of segment groups, wherein each of the plurality of segments comprises an array of a plurality of recesses having a predetermined length extending along a surface of the substrate, and wherein the plurality of recesses of each of the pair of segment groups respectively extend in differing length-wise directions; depositing a first dielectric layer on a bottom region and sidewalls of the plurality of recesses and on the surface of the substrate; depositing a first conducting layer of a first thickness over the first dielectric layer, wherein the first thickness is substantially uniform; depositing a second dielectric layer over the first conducting layer; depositing a second conducting layer of a second thickness over the second dielectric layer, wherein the second thickness is substantially uniform; removing portions of the second conducting layer and the second dielectric layer not within the plurality of recesses; and removing portions of the first conducting layer and the first dielectric layer on the surface which are not within a local region of the plurality of recesses; and electronically coupling the plurality of capacitor structures to an integrated circuit on the semiconductor die. ### Claim 19 (depends on 18) The method of claim 18, further comprising: forming a first contact connected to the first conducting layer over the surface of the substrate; forming a second contact connected to the second conducting layer; and forming a third contact connected to the substrate within the local region of the plurality of recesses, wherein electronically coupling the plurality of capacitor structures to the integrated circuit on the semiconductor die further comprises electronically connecting the first contact, second contact, and third contact to the integrated circuit. ### Claim 20 (depends on 18) The method of claim 18, wherein electronically coupling the plurality of capacitor structures to the integrated circuit comprises forming one or more of a wire bond, a through silicon via, or a bond pad between the plurality of capacitor structures and the integrated circuit.