# US 2019/0244918 A1 · Methods of forming connector pad structures, interconnect structures, and structures thereof

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- Number: US 2019/0244918 A1
- Document ID: US20190244918A1
- Status: Published application
- Kind: A1
- Application number: 16/390,628
- Filed: 2019-04-22
- Published: 2019-08-08
- Earliest claimed: 2015-07-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chia-Lun Chang; Chung-Shi Liu; Hsiu-Jen Lin; Hsien-Wei Chen; Ming-Da Cheng; Wei-Yu Chen
- Web page: https://patentgrep.com/patent/US20190244918A1

## CPC

- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 74/014: {using batch processing}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01257: {by reflowing}
- H10W 72/01271: {Cleaning, e.g. oxide removal or de-smearing}
- H10W 72/019: {of bond pads}
- H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/283: {Reinforcing structures, e.g. bump collars}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/551: {Materials of bond wires}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 72/987: {Flow barriers}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

## Claims

### Claim 1

A semiconductor device comprising:
an integrated circuit die;
a metallization pad electrically connected to the integrated circuit die, an upper surface of the metallization pad having an average surface roughness of 0.18 μm to 0.25 μm;
a connector on a first portion of the upper surface of the metallization pad;
a polymer layer on a second portion of the upper surface of the metallization pad and a sidewall of the metallization pad; and
an intermetallic compound (IMC) between the first portion of the upper surface of the metallization pad and the connector.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the metallization pad is in a dielectric layer, and wherein the polymer layer extends between a sidewall of the metallization pad and a sidewall of the dielectric layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1 further comprising:
a first redistribution line (RDL) on a first side of the integrated circuit die and electrically connected the metallization pad, the metallization pad is on the first side of the integrated circuit die;
a molding compound encapsulating the integrated circuit die;
a though via extending through the molding compound;
a second RDL on a second side of the integrated circuit die and electrically connected to the first RDL through the through via, the second side of the integrated circuit die being opposite the first side; and
a second metallization pad electrically connected to the second RDL, the second metallization pad is on the second side of the integrated circuit die.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the second metallization pad has an average surface roughness of 0.18 μm to 0.25 μm.

### Claim 5 (depends on 3)

The semiconductor device of claim 3 further comprising:
a second connector on a first portion of a lower surface of the second metallization pad; and
a second IMC between the first portion of the lower surface of the second metallization pad and the second connector.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, herein the polymer layer covers all edges of the metallization pad.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the polymer layer completely encircles the connector in a top down view.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the polymer layer extends to a bottommost surface f the metallization pad.

### Claim 9

A package comprising:
an integrated circuit die;
a molding material encapsulating integrated circuit die;
a first metallization pad electrically connected to the integrated circuit die by a redistribution structure, an average surface roughness of a lateral surface of the first metallization pad is in the range of 0.18 μm to 0.25 μm;
a second metallization pad electrically connected to the first metallization pad by a through via, the second metallization pad is on an opposing side of the integrated circuit die as the first metallization pad, the through via extends through the molding material;
a first connector on the first metallization pad; and
a second connector on the second metallization pad.

### Claim 10 (depends on 9)

The package of claim 9, wherein an average surface roughness of a lateral surface of the second metallization pad is in the range of 0.18 μm to 0.25 μm.

### Claim 11 (depends on 10)

The package of claim 10, wherein the second connector contacts the lateral surface of the second metallization pad.

### Claim 12 (depends on 10)

The package of claim 10 further comprising a first intermetallic compound (IMC) between the lateral surface of the first metallization pad and the first connector.

### Claim 13 (depends on 9)

The package of claim 9 further comprising a polymer layer contacting the lateral surface of the first metallization pad.

### Claim 14 (depends on 13)

The package of claim 13, wherein the polymer layer extends below the lateral surface of the first metallization pad.

### Claim 15

A method comprising:
forming a metallization pad electrically connected to an integrated circuit die;
exposing an upper surface of the metallization pad to a plasma treatment, the plasma treatment increases a surface roughness of the upper surface of the metallization pad;
depositing a polymer layer on a first portion of the upper surface of the metallization pad; and
forming a connector on a second portion of the upper surface of the metallization pad.

### Claim 16 (depends on 15)

The method of claim 15, wherein after applying the plasma treatment, an average surface roughness of the upper surface of the metallization pad is in the range of 0.18 μm to 0.25 μm.

### Claim 17 (depends on 15)

The method of claim 15, wherein the polymer layer is deposited after exposing the upper surface of the metallization pad to the plasma treatment.

### Claim 18 (depends on 15)

The method of claim 15 further comprising forming an intermetallic compound (IMC) between the connector and the second portion of the upper surface of the metallization pad.

### Claim 19 (depends on 15)

The method of claim 15, wherein depositing the polymer layer further comprises depositing the polymer layer along a sidewall of the metallization pad.

### Claim 20 (depends on 15)

The method of claim 15, wherein forming the metallization pad comprises forming the metallization pad in a dielectric layer, and wherein depositing the polymer layer comprises depositing the polymer layer between a sidewall of the metallization pad and a sidewall of the polymer layer.