# US 2019/0244907 A1 · Semiconductor package structure and method for manufacturing the same

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- Number: US 2019/0244907 A1
- Document ID: US20190244907A1
- Status: Published application
- Kind: A1
- Application number: 15/889,004
- Filed: 2018-02-05
- Published: 2019-08-08
- Earliest claimed: 2018-02-05
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Guo-Cheng LIAO; Chia Ching CHEN; Yi Chuan DING
- Web page: https://patentgrep.com/patent/US20190244907A1

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.

## Claims

### Claim 1

A semiconductor package structure, comprising:
a first conductive structure comprising a first redistribution layer;
a first semiconductor component disposed on the first conductive structure;
a second conductive structure comprising a second redistribution layer and electrically connected to the first conductive structure;
a second semiconductor component disposed on the second conductive structure, wherein the second semiconductor component and the first conductive structure are disposed side-by-side; and
a first encapsulant covering the first semiconductor component and the first conductive structure, wherein a lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.

### Claim 2 (depends on 1)

The semiconductor package structure of claim 1, wherein the first encapsulant further covers the lateral surface of the first conductive structure.

### Claim 3 (depends on 1)

The semiconductor package structure of claim 1, wherein an area of the second conductive structure is greater than an area of the first conductive structure, and the second conductive structure contacts the first conductive structure.

### Claim 4 (depends on 1)

The semiconductor package structure of claim 1, wherein a line width and a line space (L/S) of the first redistribution layer of the first conductive structure is smaller than a line width and a line space (L/S) of the second redistribution layer of the second conductive structure.

### Claim 5 (depends on 1)

The semiconductor package structure of claim 1, wherein first encapsulant further covers the second semiconductor component and the second conductive structure.

### Claim 6 (depends on 5)

The semiconductor package structure of claim 5, wherein the lateral surface of the first encapsulant is substantially coplanar with a lateral surface of the second conductive structure.

### Claim 7 (depends on 1)

The semiconductor package structure of claim 1, further comprising a second encapsulant covering the second semiconductor component and the second conductive structure.

### Claim 8 (depends on 7)

The semiconductor package structure of claim 7, wherein a lateral surface of the second encapsulant is substantially coplanar with a lateral surface of the second conductive structure.

### Claim 9 (depends on 7)

The semiconductor package structure of claim 7, wherein the second encapsulant further covers the first encapsulant.

### Claim 10 (depends on 1)

The semiconductor package structure of claim 1, wherein the first semiconductor component includes a plurality of conductive bumps electrically connected to the first conductive structure.

### Claim 11 (depends on 1)

The semiconductor package structure of claim 1, further comprising a shielding layer covering the first encapsulant and electrically connected to the second conductive structure.

### Claim 12 (depends on 11)

The semiconductor package structure of claim 11, wherein the second conductive structure further comprises a ground pad, and the shielding layer is electrically connected to the ground pad of the second conductive structure.

### Claim 13 (depends on 1)

The semiconductor package structure of claim 1, further comprising an interposer interposed between the first conductive structure and the second conductive structure, wherein the interposer includes a plurality of through vias electrically connecting the first conductive structure and the second conductive structure.

### Claim 14

(canceled)

### Claim 15

A method for manufacturing a semiconductor package structure, comprising:
(a) forming a base wiring structure on a first carrier, wherein the base wiring structure includes a first redistribution layer;
(b) singulating the base wiring structure to form a plurality of first conductive structures;
(c) disposing the first conductive structures on a second carrier;
(d) disposing a first semiconductor component on one first conductive structure of the first conductive structures;
(d1) disposing a second semiconductor component on the second carrier, wherein the second semiconductor component and the one first conductive structure are disposed side-by-side; and
(e) forming a first encapsulant to cover the first semiconductor component and a lateral surface of the first conductive structure, wherein the first encapsulant further covers the second semiconductor component.

### Claim 16 (depends on 15)

The method of claim 15, wherein after (e), the method further comprises:
(f) removing the second carrier;
(g) forming an outer wiring structure on the first conductive structure and the first encapsulant, wherein the outer wiring structure includes a second redistribution layer; and
(h) singulating the outer wiring structure and the first encapsulant.

### Claim 17

A method for manufacturing a semiconductor package structure, comprising:
(a) forming a base wiring structure on a first carrier, wherein the base wiring structure includes a first redistribution layer;
(b) singulating the base wiring structure to form a plurality of first conductive structures;
(c) disposing the first conductive structures on a second carrier;
(d) disposing a first semiconductor component on one first conductive structure of the first conductive structures;
(e) forming a first encapsulant to cover the first semiconductor component and a lateral surface of the first conductive structure;
(f) removing the second carrier;
(g) singulating the first encapsulant to form a plurality of unit packages;
(h) disposing the unit packages on a third carrier;
(i) disposing a second semiconductor component on the third carrier; and
(j) forming a second encapsulant to cover the second semiconductor component and the unit packages.

### Claim 18 (depends on 17)

The method of claim 17, wherein after (h), the method further comprises:
(h1) forming a shielding layer to cover the unit packages.

### Claim 19 (depends on 18)

The method of claim 18, wherein the shielding layer contacts the third carrier.

### Claim 20 (depends on 17)

The method of claim 17, wherein after (j), the method further comprises:
(k) removing the third carrier;
(l) forming an outer wiring structure on the unit packages and the second encapsulant, wherein the outer wiring structure includes a second redistribution layer; and
(m) singulating the outer wiring structure and the second encapsulant.