# US 2019/0244902 A1 · Split rail structures located in adjacent metal layers

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- Number: US 2019/0244902 A1
- Document ID: US20190244902A1
- Status: Published application
- Kind: A1
- Application number: 16/384,673
- Filed: 2019-04-15
- Published: 2019-08-08
- Earliest claimed: 2016-10-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chia-Tien Wu; Hsiang-Wei Liu; Wei-Chen Chu
- Web page: https://patentgrep.com/patent/US20190244902A1

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10P 76/40: of masks comprising inorganic materials
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0698: {Local interconnections}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/427: {Power or ground buses}
- H10W 20/43: Layouts of interconnections
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a first rail that extends in a first direction;
a second rail that extends in the first direction;
a plurality of first metal lines disposed between the first rail and the second rail in a top view, wherein the first metal lines each extends in the first direction;
a third rail that extends in the first direction;
a fourth rail that extends in the first direction;
a plurality of second metal lines disposed between the third rail and the fourth rail in the top view, wherein the second metal lines each extends in a second direction different from the first direction;
a plurality of first vias that are disposed between the first rail and the third rail; and
a plurality of second vias that are disposed between the second rail and the fourth rail.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second direction is perpendicular to the first direction.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein:
the first rail and the second rail are each located in a first metal layer; and
the third rail and the fourth rail are each located in a second metal layer that is disposed over the first metal layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first metal layer is a metal-0 layer, and the second metal layer is a metal-1 layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein:
the first vias are uniformly spaced apart from one another in the top view; and
the second vias are uniformly spaced apart from one another in the top view.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first vias and the second vias each have a greater dimension in the first direction than in the second direction.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a number of the first vias is equal to a number of the second vias.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein one of the first vias overlaps with a middle segment of the first rail in the top view, another one of the first vias overlaps with a first end segment of the first rail in the top view, and a further one of the first vias overlaps with a second end segment of the first rail, the second end being opposite the first end in the top view.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein:
borders of the first rail are surrounded by borders of the third rail in the top view; and
borders of the second rail are surrounded by borders of the fourth rail in the top view.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein:
each of the first metal lines intersect with two or more of the second metal lines in the top view; and
each of the second metal lines intersect with two or more of the first metal lines in the top view.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein:
the first rail or the second rail has a first dimension measured in the second direction;
the first metal lines each have a second dimension measured in the second direction; and
the first dimension is at least several times larger than the second dimension.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein:
the third rail or the fourth rail has a third dimension measured in the second direction;
the second metal lines each have a fourth dimension measured in the first direction; and
the third dimension is larger than the fourth dimension.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the first rail and the third rail are each a voltage rail or a ground rail.

### Claim 14

A semiconductor device, comprising:
a first rail structure and a second rail structure that each extends in a first direction in a top view, wherein the first rail structure or the second rail structure includes a power rail or a ground rail of an Integrated Circuit (IC);
a plurality of first metal lines disposed between the first rail structure and the second rail structure in the top view, wherein the first metal lines each extends in the first direction in the top view;
a third rail structure and a fourth rail structure that each extends in the first direction in the top view, wherein the third rail structure is located over the first rail structure in a side view, and wherein the fourth rail structure is located over the second rail structure in the side view;
a plurality of second metal lines disposed between the third rail structure and the fourth rail structure in the top view, wherein the second metal lines each extends in a second direction different from the first direction in the top view, and wherein each of the second metal lines partially overlaps with at least one of the first metal lines in the top view;
a plurality of first vias that electrically connect the first rail structure to the third rail structure, wherein the first vias are spread out in the top view with respect to the first rail structure or with respect to the third rail structure; and
a plurality of second vias that electrically connect the second rail structure to the fourth rail structure, wherein the second vias are spread out in the top view with respect to the second rail structure or with respect to the fourth rail structure.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein:
the second direction is perpendicular to the first direction;
the first rail structure and the second rail structure are each located in a first interconnect layer; and
the third rail structure and the fourth rail structure are each located in a second interconnect layer that is one level above the first interconnect layer.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein:
a number of the first vias or a number of the second vias is at least three; and
the first vias and the second vias each have a greater dimension in the first direction than in the second direction.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein:
the first rail structure is surrounded by the third rail structure in the top view; and
the second rail structure is surrounded by the fourth rail structure in the top view.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein:
the first rail structure or the second rail structure has a first dimension measured in the second direction;
the first metal lines each have a second dimension measured in the second direction, the first dimension being at least several times larger than the second dimension;
the third rail structure or the fourth rail structure has a third dimension measured in the second direction; and
the second metal lines each have a fourth dimension measured in the first direction, the third dimension being larger than the fourth dimension.

### Claim 19

A semiconductor device, comprising:
a first metal layer of a multi-layer interconnect structure, wherein the first metal layer includes:
a first rail that extends in a first direction in a top view;
a second rail that extends in the first direction in the top view; and
a plurality of first metal lines disposed between the first rail and the second rail in the top view, wherein the first metal lines each extends in the first direction in the top view;
a second metal layer of the multi-layer interconnect structure, wherein the second metal layer is located one level above the first metal layer and includes:
a third rail that extends in the first direction in the top view;
a fourth rail that extends in the first direction in the top view;
a plurality of second metal lines disposed between the third rail and the fourth rail in the top view, wherein the second metal lines each extends in a second direction in the top view, the second direction being perpendicular to the first direction;
at least three first vias that are disposed directly above the first rail and directly below the third rail in a side view; and
at least three second vias that are disposed directly above the second rail and directly below the fourth rail in the side view.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein:
the first vias are uniformly spaced apart from one another in the top view; and
the second vias are uniformly spaced apart from one another in the top view.