# US 2019/0244884 A1 · Semiconductor device

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- Number: US 2019/0244884 A1
- Document ID: US20190244884A1
- Status: Published application
- Kind: A1
- Application number: 16/126,430
- Filed: 2018-09-10
- Published: 2019-08-08
- Earliest claimed: 2018-02-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sung Young YOON; Yong Sang CHO; Sang Su HA
- Web page: https://patentgrep.com/patent/US20190244884A1

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 70/656: Fan-in layouts
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/257: {Multiple bump connectors having different materials}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor chip including a gate structure, the semiconductor chip having a first region and a second region that surrounds sides of the first region, first solder balls on the first region of the semiconductor chip and containing a first weight percent of silver, second solder balls on the first region of the semiconductor chip and containing a second weight percent of silver greater than the first weight percent, and third solder balls on the second region of the semiconductor chip and containing a third weight percent of silver less than the first weight percent.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor chip including a gate structure, the semiconductor chip having a first region and a second region that surrounds sides of the first region;
first solder balls on the first region of the semiconductor chip and containing a first weight percent of silver;
second solder balls on the first region of the semiconductor chip and containing a second weight percent of silver greater than the first weight percent; and
third solder balls on the second region of the semiconductor chip and containing a third weight percent of silver less than the first weight percent.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a redistribution layer on the first region of the semiconductor chip, electrically connected to the second solder balls, and electrically insulated from the first solder balls and the third solder balls.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2, wherein the redistribution layer includes a first redistribution layer electrically connected to one of the second solder balls, and a second redistribution layer electrically connected to another one of the second solder balls and is spaced apart from the first redistribution layer.

### Claim 4 (depends on 3)

The semiconductor device as claimed in claim 3, wherein a top surface of the gate structure includes a first part that overlaps the first redistribution layer, a second part that overlaps the second redistribution layer, and a third part between the first and second parts that does not overlap the first and second redistribution layers.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
the first solder balls have a first degree of thermal expansion,
the second solder balls have a second degree of thermal expansion greater than the first degree of thermal expansion, and
the third solder balls have a third degree of expansion less than the first degree of thermal expansion.

### Claim 6 (depends on 5)

The semiconductor device as claimed in claim 5, wherein:
the first solder balls have a first hardness,
the second solder balls have a second hardness greater than the first hardness, and
the third solder balls have a third hardness less than the first hardness.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
the first solder balls contain a fourth weight percent of tin,
the second solder balls contain a fifth weight percent of tin less than the fourth weight percent, and
the third solder balls contain a sixth weight percent of tin greater than the fourth weight percent.

### Claim 8 (depends on 7)

The semiconductor device as claimed in claim 7 wherein the first solder balls, the second solder balls, and the third solder balls all have a same copper content.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
the first solder balls contain a seventh weight percent of copper,
the second solder balls contain an eighth weight percent of copper less than the seventh weight percent, and
the third solder balls contain a ninth weight percent of copper greater than the seventh weight percent.

### Claim 10 (depends on 9)

The semiconductor device as claimed in claim 9, wherein the first solder balls, the second solder balls, and the third solder balls all have a same tin content.

### Claim 11

A semiconductor device, comprising:
a semiconductor chip including a gate structure, the semiconductor chip having a first region and a second region that surrounds sides of the first region;
a redistribution layer on the first region of the semiconductor chip;
first solder balls on the first region of the semiconductor chip, electrically insulated from the redistribution layer, and having a first degree of thermal expansion;
second solder balls on the first region of the semiconductor chip, electrically connected to the redistribution layer, and having a second degree of thermal expansion greater than the first degree of thermal expansion; and
third solder balls on the second region of the semiconductor chip, electrically insulated from the redistribution layer, and having a third degree of thermal expansion less than the first degree of thermal expansion.

### Claim 12 (depends on 11)

The semiconductor device as claimed in claim 11, wherein:
the first solder balls have a first hardness,
the second solder balls have a second hardness greater than the first hardness, and
the third solder balls have a third hardness less than the first hardness.

### Claim 13 (depends on 11)

The semiconductor device as claimed in claim 11, wherein:
the first solder balls contain a first weight percent of silver,
the second solder balls contain a second weight percent of silver greater than the first weight percent, and
the third solder balls contain a third weight percent of silver less than the first weight percent.

### Claim 14 (depends on 11)

The semiconductor device as claimed in claim 11, wherein:
the first solder balls contain a fourth weight percent of tin,
the second solder balls contain a fifth weight percent of tin less than the fourth weight percent, and
the third solder balls contain a sixth weight percent of tin greater than the fourth weight percent.

### Claim 15 (depends on 11)

The semiconductor device as claimed in claim 11, wherein:
the first solder balls contain a seventh weight percent of copper,
the second solder balls contain an eighth weight percent of copper less than the seventh weight percent, and
the third solder balls contain a ninth weight percent of copper greater than the seventh weight percent.

### Claim 16 (depends on 11)

The semiconductor device as claimed in claim 11, wherein a top surface of the gate structure does not overlap the redistribution layer.

### Claim 17

A semiconductor device, comprising:
a semiconductor chip including a gate structure, the semiconductor chip having a first region and a second region that surrounds sides of the first region;
a redistribution layer on the first region of the semiconductor chip;
first solder balls on the first region of the semiconductor chip, electrically insulated from the redistribution layer, and having a first hardness;
second solder balls on the first region of the semiconductor chip, electrically connected to the redistribution layer, and having a second hardness greater than the first hardness; and
third solder balls on the second region of the semiconductor chip, electrically insulated from the redistribution layer, and having a third hardness less than the first hardness.

### Claim 18 (depends on 17)

The semiconductor device as claimed in claim 17, wherein:
the first solder balls have a first degree of thermal expansion,
the second solder balls have a second degree of thermal expansion greater than the first degree of thermal expansion, and
the third solder balls have a third degree of expansion less than the first degree of thermal expansion.

### Claim 19 (depends on 17)

The semiconductor device as claimed in claim 17, wherein:
the first solder balls contain a first weight percent of silver,
the second solder balls contain a second weight percent of silver greater than the first weight percent, and
the third solder balls contain a third weight percent of silver less than the first weight percent.

### Claim 20 (depends on 17)

The semiconductor device as claimed in claim 17, wherein a top surface of the gate structure completely overlaps the redistribution layer.