# US 2019/0244883 A1 · Package with wall-side capacitors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0244883 A1 - Document ID: US20190244883A1 - Status: Published application - Kind: A1 - Application number: 16/341,963 - Filed: 2016-11-18 - Published: 2019-08-08 - Earliest claimed: 2016-11-18 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Jenny Shio Yin Ong; Seok Ling Lim - Web page: https://patentgrep.com/patent/US20190244883A1 ## CPC - H10W 70/657: {on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers} - H05K 1/117: {Pads along the edge of rigid circuit boards, e.g. for pluggable connectors} - H05K 3/3405: {Edge mounted components, e.g. terminals} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H05K 3/429: {Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers} - H05K 3/4602: {characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated} - H05K 3/4608: {comprising an electrically conductive base or core} - H05K 2201/09536: Buried plated through-holes, i.e. plated through-holes formed in a core before lamination - H05K 2201/0959: Plated through-holes or plated blind vias filled with insulating material - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract An apparatus is provided which comprises: a plurality of organic dielectric layers forming a substrate, a plurality of first conductive contacts on a top surface of the substrate, a plurality of second conductive contacts on a bottom surface of the substrate, a plurality of third conductive contacts on a side wall surface of the substrate, and one or more discrete capacitor(s) coupled with the third conductive contacts on the side wall surface. Other embodiments are also disclosed and claimed. ## Claims ### Claim at position 1 1-25. (canceled) ### Claim 26 An apparatus comprising: a plurality of dielectric layers forming a substrate; a plurality of first conductive contacts on a top surface of the substrate; a plurality of second conductive contacts on a bottom surface of the substrate opposite of the top surface; a plurality of third conductive contacts on a side wall surface of the substrate perpendicular to the top and bottom surfaces; and one or more discrete capacitor(s) coupled with the third conductive contacts on the side wall surface. ### Claim 27 (depends on 26) The apparatus of claim 26, further comprising a substrate core within the dielectric layers. ### Claim 28 (depends on 27) The apparatus of claim 27, further comprising the one or more discrete capacitor(s) coupled with third conductive contacts on the side wall surface on opposite sides of the substrate core. ### Claim 29 (depends on 26) The apparatus of claim 26, further comprising the one or more discrete capacitor(s) arranged with a long edge parallel to the top and bottom surfaces. ### Claim 30 (depends on 26) The apparatus of claim 26, wherein the one or more discrete capacitor(s) comprise a surface-mount device (SMD). ### Claim 31 (depends on 26) The apparatus of claim 26, wherein the one or more discrete capacitor(s) comprises a 0402 package capacitor. ### Claim 32 An apparatus comprising: one or more integrated circuit die(s); and a substrate, wherein the substrate comprises: a plurality of dielectric layers; a plurality of first conductive contacts on a top surface of the substrate, wherein the first conductive contacts are coupled with the one or more integrated circuit die(s); a plurality of second conductive contacts on a bottom surface of the substrate; a plurality of third conductive contacts on a side wall surface of the substrate; and one or more discrete capacitor(s) coupled with the third conductive contacts on the side wall surface. ### Claim 33 (depends on 32) The apparatus of claim 32, wherein the one or more discrete capacitor(s) comprise a height of greater than about 200 um. ### Claim 34 (depends on 32) The apparatus of claim 32, further comprising the one or more discrete capacitor(s) arranged with a long edge parallel to the top and bottom surfaces. ### Claim 35 (depends on 32) The apparatus of claim 32, wherein the one or more discrete capacitor(s) comprise a surface-mount device (SMD). ### Claim 36 (depends on 32) The apparatus of claim 32, further comprising the one or more discrete capacitor(s) coupled with third conductive contacts on the side wall surface on opposite sides of a substrate core. ### Claim 37 (depends on 32) The apparatus of claim 32, wherein the one or more discrete capacitor(s) comprises a 0402 package capacitor. ### Claim 38 A system comprising: a display subsystem; a wireless communication interface; and an integrated circuit package, the integrated circuit package comprising: one or more integrated circuit die(s); and a substrate coupled with the die(s), wherein the substrate comprises: a plurality of dielectric layers built upon a substrate core; a plurality of first conductive contacts on a top surface of the substrate, wherein the first conductive contacts are coupled with the one or more integrated circuit die(s); a plurality of second conductive contacts on a bottom surface of the substrate; a plurality of third conductive contacts on a side wall surface of the substrate; and one or more discrete capacitor(s) coupled with the third conductive contacts on the side wall surface. ### Claim 39 (depends on 38) The system of claim 38, further comprising a substrate core within the dielectric layers. ### Claim 40 (depends on 39) The system of claim 39, further comprising the one or more discrete capacitor(s) coupled with third conductive contacts on the side wall surface on opposite sides of the substrate core. ### Claim 41 (depends on 38) The system of claim 38, further comprising the one or more discrete capacitor(s) arranged horizontally. ### Claim 42 (depends on 38) The system of claim 38, wherein the one or more discrete capacitor(s) comprise a surface-mount device (SMD). ### Claim 43 (depends on 38) The system of claim 38, wherein the one or more discrete capacitor(s) comprises a 0402 package capacitor. ### Claim 44 A method comprising: forming a substrate, the substrate comprising: a plurality of dielectric layers; a plurality of first conductive contacts on a top surface of the substrate; a plurality of second conductive contacts on a bottom surface of the substrate; and a plurality of third conductive contacts on a side wall surface of the substrate; and attaching one or more discrete capacitor(s) to the third conductive contacts on a side wall surface of the substrate. ### Claim 45 (depends on 44) The method of claim 44, wherein forming the plurality of third conductive contacts on a side wall surface of the substrate comprises: forming vias that extend beyond an imaginary reference line; and severing along the imaginary reference line. ### Claim 46 (depends on 44) The method of claim 44, wherein attaching one or more discrete capacitor(s) to the third conductive contacts on a side wall surface of the substrate comprises: plating the third conductive contacts with a solder paste; coupling the discrete capacitor in contact with the plated contacts; and heating the solder paste. ### Claim 47 (depends on 46) The method of claim 46, wherein heating the solder paste comprises hot gas convection. ### Claim 48 (depends on 44) The method of claim 44, wherein forming a plurality of dielectric layers comprises forming organic dielectric layers on a substrate core. ### Claim 49 (depends on 48) The method of claim 48, further comprising forming third conductive contacts on a side wall surface of the substrate that span the substrate core. ### Claim 50 (depends on 44) The method of claim 44, wherein attaching one or more discrete capacitor(s) to the third conductive contacts on a side wall surface of the substrate comprises attaching a 0402 package capacitor to the third conductive contacts on a side wall surface of the substrate.