# US 2019/0244657 A1 · Semiconductor memory device managing flexible refresh skip area

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- Number: US 2019/0244657 A1
- Document ID: US20190244657A1
- Status: Published application
- Kind: A1
- Application number: 16/389,905
- Filed: 2019-04-19
- Published: 2019-08-08
- Earliest claimed: 2015-08-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Uksong Kang; Hoiju Chung
- Web page: https://patentgrep.com/patent/US20190244657A1

## CPC

- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/40622: {Partial refresh of memory arrays}
- G11C 11/40626: {Temperature related aspects of refresh operations}
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.

## Claims

### Claim 1

A memory system comprising:
a memory controller configured to generate a beginning address and an end address of a memory area of a memory cell array that is to be refreshed and does not include a refresh skip area of the memory cell array; and
a memory device comprising a refresh area storage unit configured to store the beginning address and the end address, and the memory cell array.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the memory controller is further configured to reduce a number of refresh commands that are provided to the memory device based on the refresh skip area.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein a number of word lines that are activated at the same time by each of the refresh commands when the number of the refresh commands is reduced by the memory controller is the same as a number of word lines that are activated at the same time by each of the refresh commands when the number of the refresh commands is not reduced by the memory controller are the same.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein the memory controller does not reduce a number of refresh commands that are provided to the memory device based on the refresh skip area.

### Claim 5 (depends on 4)

The memory system of claim 4, wherein a number of word lines that are activated at the same time by each of the refresh commands when the memory cell array has the refresh skip area is smaller than a number of word lines that are activated at the same time by each of the refresh commands when the memory cell array does not have the refresh skip area.

### Claim 6 (depends on 1)

The memory system of claim 1, wherein the memory controller does not reduce a number of refresh commands that are provided to the memory device based on the refresh skip area, and
a number of word lines that are activated at the same time by each of the refresh commands when the memory cell array has the refresh skip area is the same as a number of word lines that are activated at the same time by each of the refresh commands when the memory cell array does not have the refresh skip area.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein the memory controller is further configured to:
receive temperature-sensing information from the memory device, and
adjust a number of refresh commands that is provided to the memory device based on the temperature-sensing information.

### Claim 8 (depends on 1)

The memory system of claim 1, wherein the memory cell array comprises a first bank and a second bank, and
the memory controller is further configured to equally set an area of the first bank corresponding to the refresh skip area and an area of the second bank corresponding to the refresh skip area.

### Claim 9 (depends on 1)

The memory system of claim 1, wherein the memory cell array comprises a first bank and a second bank, and
the memory controller is further configured to differently set an area of the first bank corresponding to the refresh skip area and an area of the second bank corresponding to the refresh skip area.

### Claim 10 (depends on 1)

The memory system of claim 1, wherein the memory device further comprises a refresh counter having a minimum counting value corresponding to the beginning address and a maximum counting value corresponding to the end address.

### Claim 11

A memory system comprising:
a memory device comprising a memory cell array; and
a memory controller configured to set a refresh skip area of the memory cell array,
wherein the memory device is further comprises a refresh control circuit configured to control a refresh operation on a memory area of the memory cell array that is to be refreshed and does not include the refresh skip area of the memory cell array.

### Claim 12 (depends on 11)

The memory system of claim 11, wherein the memory controller is further configured to generate a beginning address and an end address of the memory area of a memory cell array that is to be refreshed, and
the memory device is configured to store the beginning address and the end address.

### Claim 13 (depends on 11)

The memory system of claim 11, wherein the memory controller is further configured to provide a refresh command to the memory device, and
the memory device further comprises a decoder configured to decode the refresh command.

### Claim 14 (depends on 11)

The memory system of claim 11, wherein the memory controller is further configured to change the refresh skip area.

### Claim 15 (depends on 11)

The memory system of claim 11, wherein the refresh skip area corresponds to a frame buffer to store data during a time period that is shorter than a refresh period of the memory device.

### Claim 16

A method of operating a memory device, the method comprising:
receiving and storing a beginning address and an end address of a memory area of a memory cell array that is to be refreshed from a memory controller;
setting a minimum counting value of a refresh counter to the beginning address and setting a maximum counting value of the refresh counter to the end address; and
receiving a refresh command from the memory controller and performing a refresh operation on the memory area that is to be refreshed and does not include a refresh skip area of the memory cell array.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
skipping a refresh operation on the refresh skip area according to the refresh command.

### Claim 18 (depends on 16)

The method of claim 16, wherein the performing the refresh operation on the memory area that is to be refreshed comprises increasing a counting value of the refresh counter when the refresh operation is done by a row unit.

### Claim 19 (depends on 18)

The method of claim 18, wherein the performing the refresh operation on the memory area that is to be refreshed further comprises resetting the counting value of the refresh counter to the minimum counting value when the counting value is greater than the maximum counting value.

### Claim 20 (depends on 16)

The method of claim 16, wherein the performing the refresh operation on the memory area that is to be refreshed comprises reducing a number of word lines that are activated at the same time by the refresh command.