# US 2019/0244656 A1 · Transition Coupling Circuitry for Memory Applications

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- Number: US 2019/0244656 A1
- Document ID: US20190244656A1
- Status: Published application
- Kind: A1
- Application number: 15/891,212
- Filed: 2018-02-07
- Published: 2019-08-08
- Earliest claimed: 2018-02-07
- Assignees: Arm Limited
- Applicants: Arm Limited
- Inventors: Yicong Li; Andy Wangkun Chen; Sharryl Renee Dettmer; Lalit Gupta; Jitendra Dasani; Yeon Jun Park; Shri Sagar Dwivedi; Fakhruddin Ali Bohra
- Web page: https://patentgrep.com/patent/US20190244656A1

## CPC

- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 11/419: Read-write [R-W] circuits
- H10B 10/15: {comprising a resistor load element}
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

## Claims

### Claim 1

An integrated circuit, comprising:
memory circuitry having a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair;
first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry; and
second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs;
wherein the first bitline pair and the second bitline pair are on a lower metal layer and the jumper bitline pairs are on a higher metal layer.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the first array of bitcells and the second array of bitcells are coupled to the column multiplexer circuitry through the first transition coupling circuitry.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the first array of bitcells are disposed closer to the column multiplexer circuitry than the second array of bitcells.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the second array of bitcells are coupled to the first transition coupling circuitry by way of the jumper bitline pairs and through the second transition coupling circuitry.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the first transition coupling circuitry is coupled to the first bitline pair on the lower metal layer and the jumper bitline pairs on the higher metal layer.

### Claim 6 (depends on 5)

The integrated circuit of claim 5, wherein the first transition coupling circuitry further comprises at least a portion of a multiplexer comprising:
a first transistor structure having first inputs and first outputs; and
a second transistor structure having second inputs and second outputs, wherein:
the first inputs are on the higher metal layer;
the second inputs are on the lower metal layer;
the first outputs are on the lower metal layer; and
the second outputs are on the higher metal layer.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, wherein the first transition coupling circuitry further comprises a via dot, and wherein the via dot couples the first outputs to the second outputs.

### Claim 8 (depends on 6)

The integrated circuit of claim 6, wherein the column multiplexer further comprises an additional portion of the multiplexor comprising a via dot, and wherein the via dot couples the first outputs to the second outputs.

### Claim 9 (depends on 6)

The integrated circuit of claim 6, wherein the first transistor structure comprises a first transistor transmission gate, and wherein the second transistor structure comprises a second transistor transmission gate.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, wherein the first transition coupling circuitry comprises a first via dot, and wherein the first via dot couples the first bitline pair to the jumper bitline pairs, and wherein the second transition coupling circuitry comprises a second via dot, and wherein the second via dot couples the second bitline pair to the jumper bitline pairs.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein:
the first array of bitcells comprises a first wordline control signal,
the second array of bitcells comprises a second wordline control signal,
each of the bitcells in the first array of bitcells or the second array of bitcells further comprises stored data, and
the first wordline control signal and the second wordline control signal are configured to select the stored data associated with a selected bitcell in either the first array of bitcells or the second array of bitcells to pass through the first via dot.

### Claim 12 (depends on 6)

The integrated circuit of claim 6, further comprising:
the first array of bitcells comprising a first wordline control signal;
the second array of bitcells comprising a second wordline control signal;
wherein the multiplexer further comprises a control signal configured to select either the first transistor structure or the second transistor structure; and
wherein the first wordline control signal and the second wordline control signal are configured to select bitcells in the first array and the second array concurrently.

### Claim 13

A method for manufacturing an integrated circuit, the method comprising:
fabricating memory circuitry having a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair;
fabricating first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry; and
fabricating second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs;
wherein the first bitline pair and the second bitline pair are on a lower metal layer and the jumper bitline pairs are on a higher metal layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first array of bitcells and the second array of bitcells are coupled to the column multiplexer circuitry through the first transition coupling circuitry.

### Claim 15 (depends on 13)

The method of claim 13, wherein the first array of bitcells are coupled to the column multiplexer circuitry through the first transition coupling circuitry.

### Claim 16 (depends on 13)

The method of claim 13, wherein the second array of bitcells are coupled to the first transition coupling circuitry by way of the jumper bitline pairs and through the second transition coupling circuitry.

### Claim 17 (depends on 13)

The method of claim 13, wherein the first transition coupling circuitry is coupled to the first bitline pair on the lower metal layer and the jumper bitline pairs on the higher metal layer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising fabricating at least a portion of a multiplexer disposed in the first transition coupling circuitry, the multiplexer comprising:
a first transistor structure having first inputs and first outputs; and
a second transistor structure having second inputs and second outputs, wherein the:
the first inputs are on the higher metal layer;
the second inputs are on the lower metal layer;
the first outputs are on the lower metal layer; and
the second outputs are on the higher metal layer.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
fabricating a first via dot disposed in the first transition coupling circuitry, wherein the first via dot couples the first bitline pair to the jumper bitline pairs; and
fabricating a second via dot disposed in the second transition coupling circuitry, wherein the second via dot couples the second bitline pair to the jumper bitline pairs.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
the first bitline pair comprise a first path having first resistance-capacitance (RC) characteristics,
the second bitline pair comprise a second path having second RC characteristics,
the jumper bitline pairs comprise a jumper path having jumper RC characteristics, and
a first sum of the first RC characteristics and the jumper RC characteristics is less than a second sum of the first RC characteristics and the second RC characteristics.

### Claim 21

An integrated circuit, comprising:
memory circuitry having a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair, wherein the first bitline pair is separate from the second bitline pair;
first transition coupling circuitry for accessing the first array of bitcells with the first bitline pair and a jumper bitline pair, wherein the first bitline pair is disposed in a first metal layer; and
second transition coupling circuitry for accessing the second array of bitcells with the second bitline pair and the jumper bitline pair, wherein the second bitline pair is disposed in the first metal layer, and wherein the jumper bitline pair is disposed in a second metal layer that is different than the first metal layer.