# US 2019/0244653 A1 · Semiconductor storage element, semiconductor storage device, and semiconductor system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0244653 A1 - Document ID: US20190244653A1 - Status: Published application - Kind: A1 - Application number: 16/336,175 - Filed: 2017-09-07 - Published: 2019-08-08 - Earliest claimed: 2016-10-20 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: MASANORI TSUKAMOTO - Web page: https://patentgrep.com/patent/US20190244653A1 ## CPC - G11C 11/221: {using ferroelectric capacitors} - G11C 11/22: using ferroelectric elements - G11C 11/223: {using MOS with ferroelectric gate insulating film} - G11C 11/2273: {Reading or sensing circuits or methods} - G11C 11/2275: {Writing or programming circuits or methods} - H10B 51/10: characterised by the top-view layout - H10B 51/30: characterised by the memory core region - H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors - H10D 30/0415: {of FETs having ferroelectric gate insulators} - H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs} - G11C 11/2259: {Cell access} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract [Object] To provide a semiconductor storage element that has a more reduced planar area. [Solution] A semiconductor storage element including: a memory cell transistor including a gate insulator film at least partially including ferroelectric material; and a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer. ## Claims ### Claim 1 A semiconductor storage element comprising: a memory cell transistor including a gate insulator film at least partially including ferroelectric material; and a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer. ### Claim 2 (depends on 1) The semiconductor storage element according to claim 1, wherein the memory cell transistor is a thin film transistor in which a gate electrode, and a source and a drain are provided on opposite sides across a gate insulator film. ### Claim 3 (depends on 2) The semiconductor storage element according to claim 2, wherein the memory cell transistor is a bottom gate transistor in which a gate electrode is provided below a gate insulator film. ### Claim 4 (depends on 1) The semiconductor storage element according to claim 1, wherein the selection transistor is a field effect transistor in which a gate insulator film is provided on a semiconductor substrate and a gate electrode is provided on the gate insulator film. ### Claim 5 (depends on 1) The semiconductor storage element according to claim 1, wherein a planar shape of the connection layer is a hook-like shape in which a straight line is bent at at least one or more bending points. ### Claim 6 (depends on 1) The semiconductor storage element according to claim 1, wherein the memory cell transistor and the selection transistor are provided in different planar regions when planarly viewed from the layer stack direction. ### Claim 7 (depends on 1) The semiconductor storage element according to claim 1, wherein the connection layer is provided integrally with the gate electrode of the memory cell transistor. ### Claim 8 (depends on 7) The semiconductor storage element according to claim 7, wherein the connection layer includes metal, an alloy, or a metal compound, and the gate insulator film of the memory cell transistor is provided on the connection layer. ### Claim 9 (depends on 1) The semiconductor storage element according to claim 1, wherein the selection transistor connects with a word line at a gate, and connects with a first bit line at another one of the source or the drain, and the memory cell transistor connects with a second bit line at one of a source or a drain, and connects with a power source or a ground at another one of the source or the drain. ### Claim 10 (depends on 9) The semiconductor storage element according to claim 9, wherein the other one of the source or the drain of the selection transistor, and the first bit line are connected by a contact plug provided on the drain to penetrate through in the layer stack direction. ### Claim 11 (depends on 9) The semiconductor storage element according to claim 9, wherein extending directions of the first bit line and the second bit line are parallel to each other, and an extending direction of the word line, and the extending directions of the first bit line and the second bit line are orthogonal to each other. ### Claim 12 A semiconductor storage device comprising: a plurality of semiconductor storage elements arranged in a matrix, the plurality of semiconductor storage elements each including a memory cell transistor including a gate insulator film at least partially including ferroelectric material, and a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer. ### Claim 13 A semiconductor system comprising: a storage device including a plurality of semiconductor storage elements arranged in a matrix and each including a memory cell transistor including a gate insulator film at least partially including ferroelectric material, and a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer; and an arithmetic device connected with the storage device, wherein the storage device and the arithmetic device are mounted on one semiconductor chip.