# US 2019/0244652 A1 · Multiple plate line architecture for multideck memory array

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- Number: US 2019/0244652 A1
- Document ID: US20190244652A1
- Status: Published application
- Kind: A1
- Application number: 16/387,208
- Filed: 2019-04-17
- Published: 2019-08-08
- Earliest claimed: 2017-03-27
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Ferdinando Bedeschi
- Web page: https://patentgrep.com/patent/US20190244652A1

## CPC

- G11C 11/22: using ferroelectric elements
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/2257: {Word-line or row circuits}
- G11C 11/2259: {Cell access}
- G11C 11/2273: {Reading or sensing circuits or methods}
- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- G11C 11/2253: {Address circuits or decoders}
- G11C 11/2275: {Writing or programming circuits or methods}
- H10B 53/30: characterised by the memory core region
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.

## Claims

### Claim 1

A method, comprising:
identifying a memory cell from a plurality of memory cells in a first array of memory cells and a second array of memory cells, the first array overlying the second array, wherein the memory cell is within the second array; and
accessing the memory cell of the second array via a first plate line and a second plate line, wherein the first plate line is coupled with the second plate line through an on pitch via (OPV) and the second plate line is coupled with the memory cell.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
accessing a second memory cell of the first array via the first plate line, wherein the first plate line is coupled with the second memory cell.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
activating the first plate line using a plate line decoder coupled with the first plate line, wherein accessing the memory cell of the second array is based at least in part on activating the first plate line.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first plate line is coupled with the plate line decoder through a second OPV.

### Claim 5 (depends on 3)

The method of claim 3, wherein the plate line decoder is located in a control circuit portion that is adjacent to the first array of memory cells.

### Claim 6 (depends on 3)

The method of claim 3, wherein the plate line decoder is dedicated to a set of even-numbered plate line addresses comprising a first even-numbered plate line address associated with the memory cell and a second even-numbered plate line address associated with the second memory cell.

### Claim 7 (depends on 2)

The method of claim 2, further comprising:
accessing a third memory cell of the second array via the first plate line and a third plate line different than the second plate line, wherein the first plate line is coupled with the third plate line through a third OPV and the third plate line is coupled with the third memory cell.

### Claim 8 (depends on 1)

The method of claim 1, wherein the memory cell comprises a ferroelectric container and a selector device, and wherein accessing the memory cell comprises:
activating a word line decoder coupled with the memory cell via a word line configured to concurrently access memory cells in the first array and the second three dimensional array.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
activating a digit line decoder coupled with the memory cell via a digit line configured to separately access memory cells in the first array and the second three dimensional array; and
writing to or reading from the memory cell via the digit line and based at least in part on activating the digit line decoder.

### Claim 10 (depends on 1)

The method of claim 1, wherein the accessing is based at least in part on an address of the memory cell, and wherein the first plate line and the second plate line are associated with the address of the memory cell.

### Claim 11 (depends on 1)

The method of claim 1, wherein the first array is a first three-dimensional array of ferroelectric memory cells and the second array is a second three-dimensional array of ferroelectric memory cells.

### Claim 12

A memory device, comprising:
a first array of memory cells;
a second array of memory cells, the first array overlying the second array;
a controller coupled with the first array and the second array, and operable to cause the memory device to:
identify a memory cell of the second array; and
access the memory cell of the second array via a first plate line and a second plate line, wherein the first plate line is coupled with the second plate line through an on pitch via (OPV) and the second plate line is coupled with the memory cell.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the controller is operable to cause the memory device to:
access a second memory cell of the first array via the first plate line, wherein the first plate line is coupled with the second memory cell.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the controller is operable to cause the memory device to:
activate the first plate line using a plate line decoder coupled with the first plate line, wherein accessing the memory cell of the second array is based at least in part on activating the first plate line.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the first plate line is coupled with the plate line decoder through a second OPV.

### Claim 16 (depends on 14)

The memory device of claim 14, wherein the plate line decoder is located in a control circuit portion adjacent to the first array.

### Claim 17 (depends on 14)

The memory device of claim 14, wherein the plate line decoder is associated with even-numbered plate line addresses and excludes odd-numbered plate line addresses, the even-numbered plate line addresses comprising an even-numbered first plate line address associated with the memory cell and an even-numbered second plate line address associated with the second memory cell.

### Claim 18 (depends on 13)

The memory device of claim 13, wherein the controller is operable to cause the memory device to:
access a third memory cell of the second array via the first plate line and a third plate line, wherein the first plate line is coupled with the third plate line through a third OPV and the third plate line is coupled with the third memory cell.

### Claim 19 (depends on 12)

The memory device of claim 12, wherein the memory cell comprises a ferroelectric container and a selector device, and wherein accessing the memory cell comprises:
activating a word line decoder coupled with the memory cell via a word line configured to concurrently access memory cells in the first array and the second array.

### Claim 20

A method, comprising:
identifying a memory cell of a second deck of a first memory tile of a plurality of memory tiles; and
accessing the memory cell via a global plate line in a first deck that is above the second deck and via a local plate line in the second deck, wherein the global plate line extends across two or more memory tiles of the plurality of memory tiles, and wherein the local plate line is associated with the first memory tile and is coupled with the global plate line through an on pitch via (OPV).