# US 2019/0244641 A1 · Self-referencing sensing schemes with coupling capacitance

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- Number: US 2019/0244641 A1
- Document ID: US20190244641A1
- Status: Published application
- Kind: A1
- Application number: 15/892,118
- Filed: 2018-02-08
- Published: 2019-08-08
- Earliest claimed: 2018-02-08
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Mahdi Jamali; William A. Melton; Daniele Vimercati; Xinwei Guo; Yasuko Hattori
- Web page: https://patentgrep.com/patent/US20190244641A1

## CPC

- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/08: Control thereof
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.

## Claims

### Claim 1

An apparatus, comprising:
a memory cell;
an input/output component; and
a sense component coupled with the memory cell and the input/output component, the sense component comprising:
a sense amplifier;
a first node coupled between the sense amplifier and the memory cell; and
a second node coupled between the sense amplifier and the memory cell, wherein the second node is capacitively coupled with the first node,
wherein the sense component is configured to determine a logic state of the memory cell based at least in part on a signal at the first node and a signal at the second node.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the sense component further comprises:
a first switching component coupled between the first node and the second node, the first switching component configured to selectively adjust the capacitive coupling of the second node with the first node.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the second node is capacitively coupled with the first node through a capacitor element of the sense component.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the second node is capacitively coupled with the first node through an intrinsic capacitance between a first amplifier of the sense amplifier and a second amplifier of the sense amplifier, the intrinsic capacitance configured to capacitively couple the first node with the second node.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising a second switching component coupled between the memory cell and the first node, the second switching component configured to selectively couple the memory cell with the first node.

### Claim 6 (depends on 1)

The apparatus of claim 1, further comprising a third switching component coupled between the memory cell and the second node, the third switching component configured to selectively couple the memory cell with the second node.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the first node is capacitively coupled with a ground voltage source.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the second node is capacitively coupled with a ground voltage source.

### Claim 9

A method, comprising:
generating a first sense signal at a first node of a sense amplifier while the first node of the sense amplifier is coupled with a memory cell;
generating a second sense signal at a second node of the sense amplifier while the second node of the sense amplifier is coupled with the memory cell, wherein the second sense signal is based at least in part on the first sense signal and a capacitive coupling between the first node of the sense amplifier and the second node of the sense amplifier; and
determining a logic state stored by the memory cell based at least in part on generating the first sense signal and generating the second sense signal.

### Claim 10 (depends on 9)

The method of claim 9, wherein determining the logic state stored by the memory cell comprises:
comparing a voltage of the first node of the sense amplifier with a voltage of the second node of the sense amplifier.

### Claim 11 (depends on 9)

The method of claim 9, wherein generating the second sense signal at the second node of the sense amplifier causes a change in voltage at the first node of the sense amplifier.

### Claim 12 (depends on 9)

The method of claim 9, wherein generating the first sense signal comprises:
building a first charge along an access line that is coupled between the memory cell and the sense amplifier, wherein the first charge is based at least in part on a charge stored at the memory cell, the charge stored at the memory cell corresponding to the logic state stored by the memory cell.

### Claim 13 (depends on 9)

The method of claim 9, wherein generating the first sense signal comprises:
activating a first switching component that is coupled between the first node of the sense amplifier and the memory cell, the first switching component configured to selectively couple the first node of the sense amplifier and the memory cell.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
deactivating the first switching component after generating the first sense signal and before generating the second sense signal.

### Claim 15 (depends on 9)

The method of claim 9, wherein generating the second sense signal comprises:
building a second charge along an access line that is coupled between the memory cell and the sense amplifier, wherein the second charge is based at least in part on a charge stored at the memory cell, the charge stored at the memory cell corresponding to a reference state stored by the memory cell.

### Claim 16 (depends on 9)

The method of claim 9, wherein generating the second sense signal comprises:
activating a second switching component that is coupled between the second node of the sense amplifier and the memory cell, the second switching component configured to selectively couple the second node of the sense amplifier and the memory cell.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second switching component is deactivated during the generating of the first sense signal.

### Claim 18 (depends on 9)

The method of claim 9, further comprising:
deactivating a third switching component after generating the second sense signal and before determining the logic state stored by the memory cell, the third switching component coupled between the capacitive coupling and one of the first node of the sense amplifier or the second node of the sense amplifier, and the third switching component configured to selectively couple the capacitive coupling and the one of the first node of the sense amplifier or the second node of the sense amplifier.

### Claim 19

An apparatus, comprising:
a sense component in electronic communication with a memory cell via a first access line;
a capacitance between a first node of the sense component and a second node of the sense component; and
a controller in electronic communication with the sense component and the memory cell, wherein the controller is operable to cause the apparatus to:
generate a first sense signal at the first node of the sense component while the memory cell is coupled with the first node of the sense component;
generate a second sense signal at the second node of the sense component while the memory cell is coupled with the second node of the sense component, wherein the second sense signal is based at least in part on the generated first sense signal and the capacitance between the first node of the sense component and the second node of the sense component; and
determine a logic state stored by the memory cell based at least in part on generating the first sense signal and generating the second sense signal.

### Claim 20 (depends on 19)

The electronic memory apparatus of claim 19, wherein the memory cell comprises a capacitive memory element.

### Claim 21 (depends on 19)

The electronic memory apparatus of claim 19, wherein determining the logic state stored by the memory cell comprises:
comparing a voltage of the first node of the sense component with a voltage of the second node of the sense component.

### Claim 22 (depends on 19)

The electronic memory apparatus of claim 19, wherein generating the second sense signal at the second node of the sense component causes a change in voltage at the first node of the sense component.

### Claim 23 (depends on 19)

The electronic memory apparatus of claim 19, wherein generating the first sense signal comprises:
building a first charge along an access line that is coupled between the memory cell and the sense component, wherein the first charge is based at least in part on a charge stored at the memory cell, the charge stored at the memory cell corresponding to the logic state stored by the memory cell.

### Claim 24 (depends on 19)

The electronic memory apparatus of claim 19, wherein generating the second sense signal comprises:
building a second charge along an access line that is coupled between the memory cell and the sense component, wherein the second charge is based at least in part on a charge stored at the memory cell, the charge stored at the memory cell corresponding to a reference state stored by the memory cell.