# US 2019/0244128 A1 · Quantum circuit and method for implementing heterogeneously encoded logical bell state

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- Number: US 2019/0244128 A1
- Document ID: US20190244128A1
- Status: Published application
- Kind: A1
- Application number: 16/343,374
- Filed: 2017-10-17
- Published: 2019-08-08
- Earliest claimed: 2016-10-18
- Assignees: Electronics and Telecommunications Research Institute
- Applicants: Electronics and Telecommunications Research Institute
- Inventors: Byung-Soo CHOI; Yong-Soo HWANG
- Web page: https://patentgrep.com/patent/US20190244128A1

## CPC

- G06N 10/20: Models of quantum computing, e.g. quantum circuits or universal quantum computers
- G06N 10/70: Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

Provided is a quantum circuit for implementing a heterogeneously encoded logical Bell state encoded including a Hadamard gating circuit configured to perform Hadamard conversions on a cat state, a controlled-NOT gating circuit configured to perform CNOT operations on first and second logical qubits and conversion results of the Hadamard gating circuit, a measuring circuit configured to measure calculation results of the CNOT gating circuit, and a logical bit converter configured to convert a bit of the second logical qubit on a basis of the measured result of the measuring circuit.

## Claims

### Claim 1

A quantum circuit comprising:
a Hadamard gating circuit configured to perform Hadamard conversions on a cat state;
a controlled-NOT (CNOT) gating circuit configured to perform CNOT operations on first and second logical qubits encoded by first and second quantum error correction codes, respectively, and conversion results of the Hadamard gating circuit;
a measuring circuit configured to measure calculation results of the CNOT gating circuit; and
a logical bit converter configured to convert a bit of the second logical qubit on a basis of the measured result of the measuring circuit.

### Claim 2 (depends on 1)

The quantum circuit of claim 1, wherein a length of the cat state is equal to a sum of a length of the first logical qubit and a length of the second logical qubit.

### Claim 3 (depends on 1)

The quantum circuit of claim 1, wherein the CNOT gating circuit performs CNOT operations on the first logical qubit and a quantum state, which corresponds to the first logical qubit, of the cat state, and
the CNOT gating circuit performs CNOT operations on the second logical qubit and a quantum state, which corresponds to the second logical qubit, of the cat state.

### Claim 4 (depends on 1)

The quantum circuit of claim 1, wherein the first and second logical qubits are encoded to quantum state |+>L.

### Claim 5 (depends on 1)

The quantum circuit of claim 1, wherein the logical bit converter is configured of a Pauli X matrix or a combination of Pauli X matrices and reverses a bit of the second logical qubit.

### Claim 6 (depends on 5)

The quantum circuit of claim 5, wherein the measuring circuit outputs classical bits corresponding to the calculation results of the CNOT gating circuit, and
the logical bit converter reverses the bit of the second logical qubit, when a number of ‘1’ of the classical bits is an odd number.

### Claim 7 (depends on 6)

The quantum circuit of claim 6, further comprising:
a parity detector configured to determine whether to reverse the bit of the second logical qubit on a basis of the classical bits.

### Claim 8

A method of operating a quantum circuit configured to a logical Bell state heterogeneously encoded by different quantum error correction codes, the operation method comprising:
performing a Hadamard conversion on cat states;
performing CNOT operations on a result of the Hadamard conversion and first and second logical qubits encoded by first and second quantum error correction codes, respectively;
measuring results of the CNOT operations; and
performing a conversion on a bit of the second logical qubit on a basis of the measured results.

### Claim 9 (depends on 8)

The method of claim 8, wherein the performing of the conversion comprises reversing the bit of the second logical qubit using a Pauli X matrix or a combination of Pauli X matrices.

### Claim 10 (depends on 8)

The method of claim 8, wherein the measuring comprises measuring the calculation result to output classical bits,
wherein, when a number of ‘1’ of the classical bits is an odd number, the bit of the second logical qubit is reversed.

### Claim 11

A quantum circuit comprising:
first to third quantum circuits, each of which comprises:
a Hadamard gating circuit configured to perform Hadamard conversions on cat states;
a CNOT gating circuit configured to perform CNOT operations on first and second logical qubits encoded by first and second quantum error correction codes, respectively, and conversion results of the Hadamard gating circuit; and
a measuring circuit configured to measure calculation results of the CNOT gating circuit;
a selection circuit configured to receive a measured result of the measuring circuit of each of the quantum circuits and select a target quantum state; and
a logical bit converter configured to convert a bit of the second logical qubit output from the third quantum circuit on a basis of the selection result of the selection circuit.

### Claim 12 (depends on 11)

The quantum circuit of claim 11, wherein the CNOT gating circuit of each of the quantum circuits performs CNOT operations on the first logical qubit and a quantum state, which corresponds to the first logical qubit, of the cat state, and
the CNOT gating circuit of each of the quantum circuits performs CNOT operations on the second logical qubit and a quantum state, which corresponds to the second logical qubit, of the cat state.

### Claim 13 (depends on 11)

The quantum circuit of claim 11, wherein the selection circuit selects the target quantum state according to majority voting.

### Claim 14 (depends on 11)

The quantum circuit of claim 11, further comprising:
a plurality of quantum error correction circuits configured to perform quantum error correction operations on the first and second quantum error correction codes output from each of the quantum circuits.

### Claim 15 (depends on 11)

The quantum circuit of claim 11, wherein the first and second logical qubits input to each of the quantum circuits are encoded to quantum state |+>.

### Claim 16 (depends on 11)

The quantum circuit of claim 11, wherein the logical bit converter reverses a bit of the second logical qubit output from the third quantum circuit using a Pauli X matrix or a combination of Pauli X matrices.