# US 2019/0244091 A1 · Acceleration of neural networks using depth-first processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0244091 A1 - Document ID: US20190244091A1 - Status: Published application - Kind: A1 - Application number: 15/889,275 - Filed: 2018-02-06 - Published: 2019-08-08 - Earliest claimed: 2018-02-06 - Assignees: NEC Corporation - Applicants: NEC Laboratories Europe GmbH - Inventors: Nicolas Weber; Felipe Huici; Mathias Niepert - Web page: https://patentgrep.com/patent/US20190244091A1 ## CPC - G06N 3/04: Architecture, e.g. interconnection topology - G06N 3/08: Learning methods - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/063: using electronic means - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A method for accelerating a neural network includes identifying neural network layers that meet a locality constraint. Code is generated to implement depth-first processing for different hardware based on the identified neural network layers. The generated code is used to perform the depth-first processing on the neural network based on the generated code. ## Claims ### Claim 1 A method for accelerating a neural network, the method comprising: identifying neural network layers that meet a locality constraint; generating code to implement depth-first processing for different hardware based on the identified neural network layers; and performing the depth-first processing on the neural network based on the generated code. ### Claim 2 (depends on 1) The method according to claim 1, wherein generating the code comprises: determining one or more pre-defined building blocks from the identified neural network layers; and combining the one or more pre-defined building blocks to obtain the code. ### Claim 3 (depends on 1) The method according to claim 1, wherein the different hardware comprise central processing units (CPUs) and graphical processing units (GPUs). ### Claim 4 (depends on 3) The method according to claim 3, wherein the CPUs include fewer single instruction multiple data (SIMD) units compared to the GPUs. ### Claim 5 (depends on 1) The method according to claim 1, wherein the neural network layers include one or more of: a convolution layer, a pooling layer, or an element-wise operational layer. ### Claim 6 (depends on 1) The method according to claim 1, wherein identifying the neural network layers comprises: identifying parts of the neural network that perform a serial processing of functions that are mergeable to obtain a stack. ### Claim 7 (depends on 5) The method according to claim 5, wherein identifying the neural network layers further comprises: mapping each function in the stack to obtain at least one operation, wherein each operation has a loop type property, the loop type property designating whether the operation has a requirement for data evaluation. ### Claim 8 (depends on 7) The method according to claim 7, wherein the at least one operation comprises an accumulation operation and a normalization operation, and wherein the accumulation operation has a loop type property requiring data to be processed in a certain area and the normalization operation has a loop type property with no data requirements. ### Claim 9 (depends on 7) The method according to claim 7, wherein identifying the neural network layers further comprises: merging the at least one operation into one or more steps, wherein a step includes only one operation with a loop type property designating that the one operation has a requirement for data evaluation. ### Claim 10 (depends on 9) The method according to claim 9, wherein identifying the neural network layers further comprises: grouping the one or more steps into one or more sequences, wherein a sequence includes steps with compatible loop types. ### Claim 11 (depends on 10) The method according to claim 10, wherein the different hardware comprise central processing units (CPUs) and graphical processing units (GPUs), and wherein sequences in the one or more sequences intended for CPUs have more steps than sequences in the one or more sequences intended for GPUs. ### Claim 12 (depends on 10) The method according to claim 10, wherein the grouping the one or more steps into the one or more sequences includes determining how each step grouped in a sequence influences data requirements of the sequence so as to reduce an amount of available memory below a memory threshold. ### Claim 13 (depends on 11) The method according to claim 11, wherein a patch size is reduced based on available memory exceeding the memory threshold, the patch size being related to an amount of data input to the sequence. ### Claim 14 (depends on 13) The method according to claim 13, wherein reduction of the patch size is limited by an underutilization of the different hardware. ### Claim 15 A system for accelerating a neural network, the system comprising one or more processors which, alone or in combination, are configured to provide for execution of the following steps: identifying neural network layers that meet a locality constraint; generating code to implement depth-first processing for different hardware based on the identified neural network layers; and performing the depth-first processing on the neural network based on the generated code.