# US 2019/0243990 A1 · Separate cores to secure processes from speculative rogue cache loads > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0243990 A1 - Document ID: US20190243990A1 - Status: Published application - Kind: A1 - Application number: 16/016,254 - Filed: 2018-06-22 - Published: 2019-08-08 - Earliest claimed: 2018-02-06 - Assignees: VMware, Inc. - Applicants: VMware, Inc. - Inventors: Michael Wei; Dan Tsafrir; Nadav Amit - Web page: https://patentgrep.com/patent/US20190243990A1 ## CPC - G06F 21/54: by adding security routines or objects to programs - G06F 9/461: {Saving or restoring of program or task context} - G06F 12/0615: {Address space extension} - G06F 12/1009: using page tables, e.g. page table structures - G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) - G06F 12/1441: {for a range} - G06F 21/52: during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} - G06F 21/577: {Assessing vulnerabilities and evaluating computer system security} - G06F 21/74: operating in dual or compartmented mode, i.e. at least one secure mode - G06F 2212/1044: Space efficiency improvement - G06F 2212/1052: Security improvement - G06F 2212/151: Emulated environment, e.g. virtual machine - G06F 2212/502: using adaptive policy - G06F 2212/657: Virtual address space management - G06F 2221/034: Test or assess a computer or a system - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present disclosure addresses the meltdown vulnerability resulting from speculative execution in a multi-core processing system. The operating system (OS) can be loaded for execution on one of several processing cores (OS core), while an application can be loaded for execution on another of the processing cores (application core). The OS core uses process page tables that map the entire kernel address space to physical memory. Conversely, the application core uses pages tables that map only a portion of the kernel address space to physical memory. ## Claims ### Claim 1 A method for executing an application on a computing system, the method comprising: executing an operating system (OS) on a first processing core selected from among a plurality of processing cores in the computing system; translating virtual addresses in a first virtual address space of an application received from the first processing core using a first set of page tables that maps an entire user address space of the application and an entire kernel address space of the OS to a physical memory shared by the plurality of processing cores; executing the application on a second processing core selected from among the plurality of processing cores in the computing system; and translating virtual addresses in a second virtual address space of the application received from the second processing core using a second set of page tables that maps the entire user address space of the application and at most only a portion of the kernel address space of the OS to the physical memory. ### Claim 2 (depends on 1) The method of claim 1, wherein the first processing core always uses the first set of process page tables when translating virtual addresses in the first virtual address space of the application. ### Claim 3 (depends on 1) The method of claim 1, wherein the second processing core always uses the second set of process page tables when translating virtual addresses in the second virtual address space of the application. ### Claim 4 (depends on 1) The method of claim 1, further comprising switching execution from the second processing core to the first processing core in response to occurrence of an interrupt or an exception in the second processing core, and handling the interrupt or exception by the OS that is executing in the first processing core. ### Claim 5 (depends on 4) The method of claim 4, further comprising the OS accessing the kernel address space using the first set of page tables. ### Claim 6 (depends on 4) The method of claim 4, further comprising sending a message from the second processing core to the first processing core in response to a system call made by the application on the second processing core and handling the system call in the first processing core. ### Claim 7 (depends on 1) The method of claim 1, wherein the application is a 64-bit application. ### Claim 8 (depends on 1) The method of claim 1, wherein the first and second processing cores are based on a 64-bit architecture. ### Claim 9 A non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by a computer device, cause the computer device to: execute an operating system (OS) on a first processing core selected from among a plurality of processing cores comprising the computer device; translate virtual addresses in a first virtual address space of an application received from the first processing core using a first set of page tables that maps an entire user address space of the application and an entire kernel address space of the OS to a physical memory shared by the plurality of processing cores; execute the application on a second processing core selected from among the plurality of processing cores comprising the computer device; and translate virtual addresses in a second virtual address space of the application received from the second processing core using a second set of page tables that maps the entire user address space of the application and at most only a portion of the kernel address space of the OS to the physical memory. ### Claim 10 (depends on 9) The non-transitory computer-readable storage medium of claim 9, wherein the first processing core always uses the first set of process page tables when translating virtual addresses in the first virtual address space of the application. ### Claim 11 (depends on 9) The non-transitory computer-readable storage medium of claim 9, wherein the second processing core always uses the second set of process page tables when translating virtual addresses in the second virtual address space of the application. ### Claim 12 (depends on 9) The non-transitory computer-readable storage medium of claim 9, wherein the computer executable instructions, which when executed by the computer device, further cause the computer device to switch execution from the second processing core to the first processing core in response to occurrence of an interrupt or an exception in the second processing core, and handle the interrupt or exception by the OS that is executing in the first processing core. ### Claim 13 (depends on 12) The non-transitory computer-readable storage medium of claim 12, further comprising the OS accessing the kernel address space using the first set of page tables. ### Claim 14 (depends on 12) The non-transitory computer-readable storage medium of claim 12, wherein the computer executable instructions, which when executed by the computer device, further cause the computer device to switch execution from the second processing core to the first processing core in response to a system call made by the application on the second processing core and handle the system call in the first processing core. ### Claim 15 A computer apparatus comprising: a plurality of processing cores; a physical memory shared by the plurality of processing cores; and a computer-readable storage medium comprising instructions for controlling the target processor to be operable to: execute an operating system (OS) on a first processing core selected from among a plurality of processing cores; translate virtual addresses in a first virtual address space of an application received from the first processing core using a first set of page tables that maps an entire user address space of the application and an entire kernel address space of the OS to the physical memory; execute the application on a second processing core selected from among the plurality of processing cores; and translate virtual addresses in a second virtual address space of the application received from the second processing core using a second set of page tables that maps the entire user address space of the application and at most only a portion of the kernel address space of the OS to the physical memory. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the first processing core always uses the first set of process page tables when translating virtual addresses in the first virtual address space of the application. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein second processing core always uses the second set of process page tables when translating virtual addresses in the second virtual address space of the application. ### Claim 18 (depends on 15) The apparatus of claim 15, wherein the computer-readable storage medium further comprises instructions for controlling the target processor to be operable to switch execution from the second processing core to the first processing core in response to occurrence of an interrupt or an exception in the second processing core, and handle the interrupt or exception by the OS that is executing in the first processing core. ### Claim 19 (depends on 18) The apparatus of claim 18, further comprising the OS accessing the kernel address space using the first set of page tables. ### Claim 20 (depends on 18) The apparatus of claim 18, wherein the computer-readable storage medium further comprises instructions for controlling the target processor to be operable to switch execution from the second processing core to the first processing core in response to a system call made by the application on the second processing core and handle the system call in the first processing core.