System and method for improved storage access in multi core system

A non-transitory computer readable medium having stored thereon instructions for causing a processing circuitry to perform a process, the process comprising:

• assigning a unique memory space within a memory to each of a plurality of processor cores;
• initiating a shared queue pair (QP), comprising a shared send queue and a shared receive queue, between the plurality of processor cores and at least a storage, wherein the shared queue is accessible by the plurality of processor cores;
• sending an instruction on the shared send queue from a first core of the plurality of processor cores to the storage, the instruction comprising an interrupt destination on a memory space assigned to the first core;
• and
• receiving an interrupt at the interrupt destination from the storage in response to the instruction, wherein the interrupt is generated for the first core.

A system for improving multi-core processor access to storages, comprising:

• a processing circuitry;
• and
• a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:
• assign a unique memory space within a memory to each of a plurality of processor cores;
• initiate a shared queue pair (QP), comprising a shared send queue and a shared receive queue, between the plurality of processor cores and at least a storage, wherein the shared queue is accessible by the plurality of processor cores;
• send an instruction on the shared send queue from a first core of the plurality of processor cores to the storage, the instruction comprising an interrupt destination on a memory space assigned to the first core;
• and
• receive an interrupt at the interrupt destination from the storage in response to the instruction, wherein the interrupt is generated for the first core.