Microprocessor with booth multiplication

A microprocessor, performing multiplication with variable word length, comprising:

• a first acquisition register, storing an unsigned ending acquisition of a first multiplier number carried in multiplier number supply data when being operated according to a first word length;
• a third acquisition register, storing a starting acquisition of a second multiplier number carried in the multiplier number supply data when being operated according to the first word length;
• a fourth acquisition register, storing a middle acquisition of a third multiplier number carried in the multiplier number supply data when being operated according to a second word length which is longer than the first word length, wherein the middle acquisition of the third multiplier number is combined from the unsigned ending acquisition of the first multiplier number and the starting acquisition of the second multiplier number;
• and
• a partial product selection circuit, wherein:
• in the first word length, a third partial product output by the partial product selection circuit is generated by performing Booth multiplication on a multiplicand corresponding to the second multiplier number based on the content contained in the third acquisition register;
• and
• in the second word length, the third partial product output by the partial product selection circuit is generated by performing Booth multiplication on a multiplicand corresponding to the third multiplier number based on the content contained in the fourth acquisition register.