Delay based comparator

A delay circuit, comprising:

• a first inverter coupled to a first transistor and a second transistor, the first inverter configured to receive a first intermediate delayed clock signal and generate a positive delayed clock signal to be received by a first negative-AND (NAND) gate of a comparator;
• a second inverter coupled to a third transistor and a fourth transistor, the second inverter configured to receive a second intermediate delayed clock signal and generate a negative delayed clock signal to be received by a second NAND gate of the comparator;
• and
• a pair of cross-coupled capacitors coupled to the first and second inverters.

A comparator, comprising:

• a differential input pair of transistors including a first input transistor and a second input transistor;
• and
• a delay circuit that includes:
• a first inverter coupled to a first transistor and a second transistor, the first inverter configured to receive a first intermediate delayed clock signal and generate a positive delayed clock signal to be received by the first input transistor;
• a second inverter coupled to a third transistor and a fourth transistor, the second inverter configured to receive a second intermediate delayed clock signal and generate a negative delayed clock signal to be received by the second input transistor;
• and
• a pair of cross-coupled capacitors coupled to the first and second inverters.

An analog-to-digital converter (ADC) comprising:

• a comparator, the comparator comprising:
• a pair of back-to-back negative-AND (NAND) gates;
• and
• a delay circuit coupled to the pair of back-to-back NAND gates, the delay circuit configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage,
• wherein each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal;
• wherein the input voltage is a differential signal that includes a positive input signal and a negative input signal;
• wherein the delay circuit is further configured to receive a differential reference signal that includes a positive reference signal and a negative reference signal;
• wherein the delay circuit includes:
• a first transistor configured to receive the positive input signal;
• a second transistor in parallel with the first transistor, the second transistor configured to receive the negative reference signal;
• a third transistor configured to receive the negative input signal;
• and
• a fourth transistor in parallel with the third transistor, the fourth transistor configured to receive the positive reference signal.