Management of Processor Performance Based on User Interrupts
AssigneeIntel Corporation
InventorsJacob Jun Pan, Ashok Raj, Srinivas Pandruvada
Life of this patent
Estimating the term…
Abstract
In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a plurality of processing engines (PEs);
- a power control unit;
- an input/output memory management unit (IOMMU) to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit, the notification indicating the destination PE for the user interrupt, the power control unit to adjust a performance state of the destination PE in response to the notification of the user interrupt.
A method comprising:
- determining, by an input/output memory management unit (IOMMU), a destination processing engine (PE) for a user interrupt;
- sending, by the IOMMU, the user interrupt directly to the determined destination PE;
- sending, by the IOMMU, a notification to a power control unit;
- and
- adjusting, by the power control unit, a performance state of the determined destination PE in response to the notification from the IOMMU.
A system comprising:
- a processor comprising a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU), the IOMMU to:
- determine a destination PE for a user interrupt based on mapping data of the IOMMU;
- send the user interrupt directly to the destination PE;
- and
- send a user interrupt notification to the power control unit, the power control unit to adjust a performance state of the destination PE in response to the user interrupt notification;
- and
- a system memory coupled to the processor.
Dependencies are inferred from the claim text.