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US 2019/0199455 A1Published application
Clutter rejecting built in test for assignment-based aesa systems
AssigneeRaytheon Company
InventorsLarisa Angelique Natalya Stephan, David W. Tang, David O. Lahti
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Abstract
Methods and apparatus to provide clutter rejecting built-in-test and/or fault isolation of individual array elements in assignment-based AESAs. BIT beam states for array element testing can be stored in AESA memory for rapid assignment sequencing of RF waveform generators and receive processing. Simultaneously transmitted signals for BIT sequences have unique signal characteristics that allow test signal clutter rejection on the receive side processing.
Claims19
A method, comprising:
- performing built-in-test (BIT) of array elements in first and second arrays in an assignment-based active electronically scanned array (AESA) by:
- receiving assignments for at least one BIT sequence from pre-determined BIT assignments each of which is mapped to a beamstate, wherein the assignments correspond to generating multiple simultaneous transmit signals having differing characteristics to provide clutter rejection by the second array;
- configuring one or more elements of the first array for transmitting pulses corresponding to the at least one BIT sequence;
- configuring one or more elements of the second array for receiving the pulses corresponding to the at least one BIT sequence;
- transmitting the pulses by the first array corresponding to the at least one BIT sequence;
- receiving the transmitted pulses at the second array for the at least one BIT sequence;
- and
- processing the received pulses for the at least one BIT sequence to detect failures associated with one or more of the elements in the first array and/or the elements in the second array.
5 more elements
A system, comprising:
- an antenna controller configured to perform built-in-test (BIT) of array elements in first and second arrays in an assignment-based active electronically scanned array (AESA), the antenna controller configured to:
- perform built-in-test (BIT) of array elements in first and second arrays in an assignment-based active electronically scanned array (AESA) by:
- receiving assignments for at least one BIT sequence from pre-determined BIT assignments each of which is mapped to a beamstate, wherein the assignments correspond to generating multiple simultaneous transmit signals having differing characteristics to provide clutter rejection by the second array;
- configuring one or more elements of the first array for transmitting pulses corresponding to the at least one BIT sequence;
- configuring one or more elements of the second array for receiving the pulses corresponding to the at least one BIT sequence;
- transmitting the pulses by the first array corresponding to the at least one BIT sequence;
- receiving the transmitted pulses at the second array for the at least one BIT sequence;
- and
- processing the received pulses for the at least one BIT sequence to detect failures associated with one or more of the elements in the first array and/or the elements in the second array.
6 more elements
A system, comprising:
- first and second arrays that are collocated, each of the first and second arrays comprising a respective waveform generator and a receive module;
- an antenna controller coupled to the first and second arrays, the respective waveform generators and the receiver modules, the antenna controller configured to perform built-in-test (BIT) of array elements in the first and second arrays in an assignment-based active electronically scanned array (AESA), the antenna controller configured to:
- generate and send waveform generator parameters to the respective waveform generators which generates RF pulse information and assignments commands for transmission,
- generate assignments for at least one BIT sequence from pre-determined BIT assignments each of which is mapped to a beamstate, wherein the assignments are sent to a first array which will be transmitting RF signals;
- configure one or more elements of the first array for transmitting pulses corresponding to the at least one BIT sequence such that each of the pulses has different characteristics to provide clutter rejection;
- configure one or more elements of the second array for receiving the pulses corresponding to the at least one BIT sequence;
- generate information to control transmission of the pulses by the first array corresponding to the at least one BIT sequence;
- generate information to control receiving of the transmitted pulses at the second array for the at least one BIT sequence;
- and
- process the received pulses for the at least one BIT sequence to detect failures associated with one or more of the elements in the first array and/or the elements in the second array.
7 more elements
Dependencies are inferred from the claim text.