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US 2019/0199371 A1Published application
Probability-based optimization of soc power
AssigneeSeagate Technology LLC
InventorsNitin Kumar Chhabra, Rohit Halba, Shashi Kumar Shaw, Shrikrishna Nana Mehetre
Life of this patent
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Abstract
A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.
Claims20
A method comprising:
- for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC;
- and
- carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.
A method comprising:
- receiving a number of channels to be employed in a system on chip (SoC);
- determining a number of bits N for the SoC based on the number of channels and based on a number of bits per channel;
- receiving warranty information for the SoC;
- and
- calculating, based on the bits N and the warranty information, a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC.
2 more elements
A computer-readable storage medium having encoded therein computer-executable instructions for causing a computing system programmed thereby to perform a method comprising:
- for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC;
- and
- carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.
Dependencies are inferred from the claim text.