Master/slave frequency locked loop

A method for compensating a clock signal in an integrated circuit comprising:

• supplying a first oscillator signal from a first oscillator circuit receiving a first supply voltage;
• receiving an indication of a target frequency at a control circuit;
• generating a first frequency control signal to control a frequency of the first oscillator signal based on the target frequency and the frequency of the first oscillator signal;
• supplying a second frequency control signal to a second oscillator circuit receiving the first supply voltage and receiving a second supply voltage, the second frequency control signal based on the first frequency control signal;
• supplying a second oscillator signal from the second oscillator circuit with a frequency of the second oscillator signal based, at least in part, on the second frequency control signal;
• and
• adjusting the frequency of the second oscillator signal responsive to a voltage change associated with the second supply voltage.

An apparatus comprising:

• a master oscillator circuit coupled to a regulated supply voltage and configured to supply a master oscillator signal;
• a control circuit coupled to the master oscillator signal configured to supply a master frequency control signal to control a frequency of the master oscillator signal to a target frequency;
• and
• a slave oscillator circuit coupled to a second regulated supply voltage and a droopy supply voltage and configured to supply a slave oscillator signal having a frequency responsive to a slave frequency control signal based on the master frequency control signal and wherein the frequency of the slave oscillator signal is further responsive to a voltage change of the droopy supply voltage.