US 2019/0199362 A1Published application

Semiconductor device and test method

AssigneeLapis Semiconductor Co., Ltd.

InventorKatsuyoshi YAGI

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Abstract

A semiconductor device according to the present invention has a PLL circuit which includes: a phase comparison part that detects the phase difference between a reference signal and an oscillation signal to produce a phase difference signal indicative of the phase difference in binary and then output the produces signal to outside through a first external terminal; a voltage conversion part that applies, to a phase difference voltage node, a phase difference voltage having a voltage value corresponding to the phase difference represented by the phase difference signal; an oscillation part that produces, as an oscillation signal, a signal having a frequency depending on the phase difference voltage; and a correction circuit that supplies a correction current to the phase difference voltage node, and upon reception of a test control signal at a second external terminal, supplies a current depending on the test control signal to the phase difference voltage node as a correction current.

Claims5

Dependent claims

A semiconductor device comprising a PLL circuit configured to produce an oscillation signal in synchronism with a reference signal, and first and second external terminals, wherein

said PLL circuit includes:
a phase comparison part configured to detect a phase difference between said reference signal and said oscillation signal to produce a phase difference signal indicative of said phase difference in binary;
a voltage conversion part configured to convert said phase difference signal into a phase difference voltage having a voltage value corresponding to said phase difference represented by said phase difference signal to apply said phase difference voltage to a phase difference voltage node;
an oscillation part configured to produce, as said oscillation signal, a signal having a frequency depending on said phase difference voltage;
and
a correction circuit configured to supply a correction current for correcting said phase difference voltage to said phase difference voltage node, wherein
said phase comparison part outputs said phase difference signal through said first external terminal, and
upon reception of a test control signal through said second external terminal, said correction circuit produces a current serving as said correction current depending on said test control signal to supply the produced current to said phase difference voltage node.

5 more elements

A test method for testing a semiconductor device having first and second external terminals and a PLL circuit, the PLL circuit including:

a phase comparison part configured to detect a phase difference between a reference signal and an oscillation signal to produce a phase difference signal indicative of said phase difference in binary and supply said phase difference signal to said first external terminal;
a voltage conversion part configured to convert said phase difference signal into a phase difference voltage having a voltage value corresponding to said phase difference represented by said phase difference signal to apply the phase difference voltage to a phase difference voltage node;
an oscillation part configured to produce, as said oscillation signal, a signal having a frequency depending on said phase difference voltage;
and a correction circuit configured to supply a correction current for correcting said phase difference voltage to said phase difference voltage node and to produce, upon reception of a test control signal at said second external terminal, a current depending on said test control signal and supply the produced current as said correction current to said phase difference voltage node, the test method comprising:
a first step of supplying said test control signal to said second external terminal of said semiconductor device;
a second step of capturing said phase difference signal outputted from said first external terminal of said semiconductor device;
a third step of determining whether a pulse width of said phase difference signal is included within a specified range;
and
a fourth step of acquiring a test result indicative of said correction circuit being good when the pulse width of said phase difference signal is determined to be included within said specified range, and a test result indicative of said correction circuit being no good when said pulse width of said phase difference signal is determined to be not included within the specified range.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/232,529Filed 26 Dec 2018
Priority: JP 2017-25223427 Dec 2017
Published: 27 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03L 7/0895
The up-down pulses controlling source and sink current generators, e.g. a charge pump: details of the current generators
G01R 29/023
Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration: measuring pulse width
G01R 31/2607
Testing of individual semiconductor devices: circuits therefor
G01R 31/31725
Testing of digital circuits: timing aspects, e.g. clock distribution, skew, propagation delay