Digital delay locked loop

A digital delay locked loop for applying a phase shift to a reference timing signal, the digital delay locked loop comprising:

• first and second digitally controllable delay lines coupled in series with each other, each comprising a lead portion and a lag portion, the first digitally controllable delay line receiving a reference timing signal and the second digitally controllable delay line outputting a delayed timing signal corresponding to the reference timing signal delayed by the first and second digitally controllable delay lines;
• and
• a time to digital converter configured to evaluate a phase difference between the reference signal and the delayed timing signal and to generate a first control signal for controlling said lead portions or and a second control signal for controlling said lag portions based on the sign and magnitude of the phase difference.