US 2019/0199353 A1 · LOOK UP TABLE INCLUDING A NONVOLATILE MEMORY ELEMENT, FPGA INCLUDING THE LOOK UP TABLE, AND METHOD FOR DESIGNING THE FPGA

Abstract

A Look Up Table (LUT) includes a data storage circuit including a plurality of nonvolatile memory elements respectively corresponding to a plurality of applications, the data storage circuit being configured to select one of the plurality of nonvolatile memory elements according to an application selection signal; an amplification circuit configured to amplify a signal output from the selected nonvolatile memory element according to an enable signal output from a decoder; and a write control circuit configured to program the selected nonvolatile memory element with information corresponding to a data signal according to a write signal.

Claims23

Dependent claims

A Look Up Table (LUT), comprising:

a data storage circuit including a plurality of nonvolatile memory elements respectively corresponding to a plurality of applications, the data storage circuit being configured to select one of the plurality of nonvolatile memory elements according to an application selection signal;
an amplification circuit configured to amplify a signal output from the selected nonvolatile memory element according to an enable signal output from a decoder;
and
a write control circuit configured to program the selected nonvolatile memory element with information corresponding to a data signal according to a write signal.

1 more element

A Field Programmable Gate Array (FPGA) comprising an LUT, wherein the LUT includes a plurality of nonvolatile memory elements respectively corresponding to a plurality of applications, the LUT being configured to select one of the plurality of memory elements according to an application selection signal;

to output an output signal corresponding to information stored in the selected nonvolatile memory element according to an enable signal output from a decoder;
and to program, according to a write signal, the selected nonvolatile memory element with information corresponding to a data signal.

Dependencies are inferred from the claim text.

Facts

Application

16/107,906Filed 21 Aug 2018

Priority

KR 10-2017-017768822 Dec 2017

Published

27 Jun 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03K 19/17728
Structural details of logic blocks: reconfigurable logic blocks, e.g. lookup tables
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
H03K 19/17736
Arranged in matrix form: structural details of routing resources
H03K 19/1776
Structural details of configuration resources: for memories

Look up table including a nonvolatile memory element, fpga including the look up table, and method for designing the fpga

Life of this patent

Look up table including a nonvolatile memory element, fpga including the look up table, and method for designing the fpga

Life of this patent

Abstract

Claims23